דרושים » חשמל ואלקטרוניקה » System Integration Engineer - Maternity Leave Replacement

we are looking for a highly motivated, energetic, and self-driven engineer to join our Silicon Photonics product team.
You will work on projects collaboratively with cross-functional teams across the company, as well as develop imaginative, thorough, and practical application solutions separately.
In this position, we are looking for someone who can leverage their experience into a multifaceted technical leadership role - being an expert in our products for outbound activities, and representing the broad user base for inbound new product development.
In this position you will work at our office in Haifa, Israel.
Responsibilities:
Leading member of product development teams with engineering, representing the broad user base defining use cases and requirements, and performing post-implementation validation. Responsibility is to ensure we are implementing the right things to meet market expectations with competitive solutions.
Participate in key-design-ins acting as expert consultant, ensuring technical success, at times taking on the role of project technical leader.
Provide expert guidance to our field applications and direct customers in development of successful test solutions
Develop and deliver technical marketing presentations with clear and effective messaging
Co-develop user documentation and training for new products and features
Continually develop deep expert knowledge of our products and use models
Continually develop knowledge of semiconductor/Silicon Photonics test requirements and trends
Develop strong relationships with worldwide account teams and key customers.
Develop knowledge and expertise on semiconductor device testing.
Develop knowledge and expertise on Automated Test Equipment (ATE) - specifically the UltraFLEXplus family of testers - with a focus on our Silicon Photonics and Software product area, with addition of Digital, Serial and DC products as projects require.
Support customers on tester operation and capability.

looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.

We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results

Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

we are looking for a Electrical Post Silicon Validation HW Engineer.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
* Handle all chip validation aspects, including:
* Building validation plans.
* Performing EPSV using advanced test and measurement equipment.
* Writing tests in Python over device SDK.
* Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.

seeking a Lead Networking Architect to help define and shape the next generation of our AI-SuperNIC scale-out chip.

Scale-out communication is a critical element in building competitive systems for modern data centers. Were looking for an expert with deep networking experience to collaborate closely with our AI/ML, platform and driver software, and VLSI teams in designing an optimized scale-out networking architecture.

If youre passionate about low-latency communication and have a strong background in RoCEv2, HPC communication, and NVMe-oF, this is a unique opportunity to take on a challenging and influential role.

This is a senior, high-impact position at the forefront of technology innovation-driving the development of cutting-edge networking and AI acceleration solutions.

Responsibilities

Work closely with CTO and peer architects to define the product requirements and features of next generation ultra low-latency AI-SuperNIC scale-out chip
Lead adoption of new industry standards such as UEC, UALink while maintaining a competitive solution for RoCEv2
Establish architecture guidelines, requirements, and the division of labor between software, firmware and hardware.
Lead performance estimations, modeling, measurements, and optimizations, as well as system-level integration efforts.
Engage directly with end customers and partners to shape use cases and system solutions.

This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.

Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.

Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities

Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

we are seeking a highly skilled and motivated Field Service Engineer to be based in our Israel office. This role is primarily dedicated to supporting systems located at the facility, while also providing additional support during peak demand periods at customer sites.
The successful candidate will be responsible for maintaining and reconfiguring test systems and probers, supporting device program development, overseeing facility equipment, and coordinating with external vendors.
Key Responsibilities:
Maintain and reconfigure office-based systems and probers in alignment with device program development requirements.
Supervise facility equipment and coordinate vendor support for maintenance and repairs.
Provide technical assistance to customers and field teams, both on-site and remotely (via phone or email).
Install and upgrade test systems, including hardware options and software updates.
Diagnose and repair system issues at both facilities and customer locations.
Be available for frequent travel, including international assignments