דרושים » הנדסה » Hardware Team Lead AV Platform

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence.
We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

As a Technical Program Manager for Silicon Development, you will use your technical and management experience to lead the development and execution of complex, multidisciplinary SoC projects. You will plan programs and manage their execution from early concepts through development to tape-out and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Plan, coordinate, and deliver custom silicon products.
Assess complexity and scope out the project, generate task lists, build a project timeline and work with the teams to make it into reality.
Lead the data-driven schedules and milestones, track the progress, proactively identify potential future issues, and identify mitigations with the team leaders.
Drive technical, budgetary, and schedule trade-off discussions with cross-functional teams.
Manage project execution and issues through design, development, test, manufacturing, deployment and sustaining activities for silicon and hardware products.

Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.

We are our company's Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations).
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.

A Senior Security Engineer is expected to be proficient in multiple domains. This is a leadership role within the Annapurna security team and you will be sought out for advice on technical and business issues. Efficient time management skills are required along with the ability to deliver results in the face of uncertainty. A Senior Security Engineer will proactively share knowledge across the community and will be a key company resource in one or more of the core areas of security. He will lead security reviews of large projects while setting standards and defining best practices for our Security teams.

Engineers in this role must show exemplary judgment in making technical trade-offs between short versus long term security and business goals. They must also demonstrate resilience and navigate difficult situations with composure and tact. A broad understanding of the business and its interconnections is required. This position will also provide training, advice, and mentorship to other engineers throughout us.

Plan the verification of digital design blocks by understanding the design specification, and interacting with design engineers to identify important verification scenarios.
Lead a team of chip engineers. Plan tasks, allocate people, and hold verification design/code reviews.
Perform code development for critical verification features and capabilities.
Work with system, software, design, and physical implementation stakeholders to make technical decisions and represent project status throughout the development process.
Lead design verification efforts and work with external and internal partners.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

We are looking for a team lead who brings both managerial and technical skills to lead the AdTech team within our acquisition software group.
Your primary focus is your team and the people in it, and we expect you to build a great team with high performing culture and values.
The key responsibility for this role is to lead a strong team of 10 cross-functional software engineers, focusing on the advertising technology and data domains.
Advertising technology domain: Focuses on analyzing campaign data for performance optimization and ensuring ad quality. Using data-driven insights, the team collaborates with user activity and marketing to drive targeted advertising and maximize ROI.
Data Domain: Focuses on data integration, reporting, and analytics, creating dashboards and reports that turn raw data into actionable insights. The relevant team members (BI engineers) ensure data quality and accessibility across departments, empowering real-time, data-driven decision-making.
What youll do:
Continuously inspire and develop your team of highly skilled engineers
Evangelize best engineering practices focusing on Agile\Scrum.
Collaborate and work closely with the marketing team, other development teams, product managers, and also with Google teams
Play a key role in architectural and strategic decisions - working on a distributed system and taking it to the next level (microservices system), GCP cloud
Work with the recruiting team to attract and retain high-quality talent
We offer a 3+2 hybrid work policy.
Work is located at the Haifa R&D Center.