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Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for an experienced Design Verification engineer to join our DFT team and help establish and grow DFT DV activity in the Cisco SiliconOne DFT team. This role is relevant for engineers with experience in DV roles, either in DFT DV or in other verification domains, who are interested in becoming familiar with DFT design, verification methodologies, and the challenges of validating testability features in advanced silicon.

Your Impact
Lead and drive DFT verification activities within the Cisco SiliconOne DFT team.

Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.

Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.

Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.

Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.

Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.

Help bridge between general DV methodologies and DFT-specific design and verification needs.

As a Project Manager, you will support multiple ASIC development programs by coordinating execution, tracking deliverables, and enabling collaboration across engineering teams. You will strengthen operational excellence through AI-based automation and tracking solutions. Your work will help teams identify risks and dependencies early, maintain alignment, and deliver programs successfully.

Support Program Managers throughout each phase of ASIC program execution.
Track milestones, action items, dependencies, risks, deliverables, status reports, dashboards, and execution metrics across multiple projects.
Coordinate activities among ASIC, Software, and Business Operations teams, including global stakeholders.
Drive follow-up and accountability to ensure project actions are completed on time.
Develop AI-powered tracking tools and automation solutions that improve project visibility, streamline processes, and strengthen program management methodologies.
Collaborate with engineering and operations teams to maintain alignment and support successful program delivery.

Technical Leadership: Provide authority guidance within the Splunk security domain, exhibiting deep expertise in SIEM, SOAR, and Observability integrations.

Strategic Advisory: Lead sophisticated, multi-functional security projects, acting as a trusted partner to CISO and IT leadership.

Solution Delivery: Lead the strategic planning, compose, and implementation of tailored Splunk security architectures to mitigate risk and maximize technology investments.

AI-Driven Security: Apply sophisticated AI and automation tools to optimize security operations, automate incident response, and improve detection efficacy.

Customer Management: Develop and maintain high-value relationships, ensuring technical alignment with customer security objectives.

Documentation Excellence: Define and implement documentation standards for sophisticated security deployments, ensuring transparency and structure for technical assets.

Authority Support: Build and apply advanced simulation environments; provide expert support for sophisticated security issues and platform challenges.

Mentorship & Growth: Build technical skills across the team, serving as a domain expert on Plan, Design, Implement, and Optimize (PDIO) methodologies.

Product Influence: Synthesize customer feedback to prioritize and advocate for Splunk product and service improvements.

Innovation: Apply expertise in security orchestration, automation, and AI Ops to deliver innovative, scalable customer outcomes.

Intellectual Capital: Lead the creation of digital assets, procedures, and standardized methodologies for Splunk security engagements.

multi-functional Partnership: Collaborate with Product Management to track security trends, influence service offers, and share actionable customer insights.

We are excited to announce that the Cisco Silicon One team is undergoing rapid growth, and we are looking for a Senior C++ Software Developer.

Your Impact

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.

You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.

Responsibilities:
As a member of the Package Design team, you will:

Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing support.

Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.

Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.

Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.

Assist in developing and improving package design methodologies, flows, and best practices.

Contribute to debugging, issue resolution, and package bring‑up activities as needed.

As a Software Engineering Technical Leader, you will drive the technical vision and execution for complex security policy and access solutions that safeguard enterprise networks globally. You will leverage your deep expertise in systems programming using C, C++, and Java to architect and develop robust, scalable software. By providing technical leadership, you will mentor peers, guide architectural decisions, and foster a culture of innovation and continuous improvement within the team. Your work will directly contribute to Cisco's mission by ensuring our network access solutions are secure, programmable, and highly reliable. You will also champion software programmability and integrate automation and orchestration practices to streamline development and enhance product performance, ultimately empowering our customers to connect with confidence.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.

Contribute to physical synthesis, place and route, optimization, and timing closure for complex VLSI designs.
Support design floor planning and implementation planning in collaboration with senior physical design engineers.
Analyze timing, congestion, power, area, and design-rule issues and help drive them toward closure.
Work with physical design verification flows, including LVS and DRC, to support clean implementation handoff.
Partner with cross-functional teams to debug implementation issues and improve backend flow quality.

Our HW team in Israel is looking for an experienced system/board designer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:

Perform board bring-up, hardware validation, characterization, and system-level debugging in the lab.

Debug issues involving power, signal integrity, interfaces, components, firmware interactions, and system behavior.

Support productization, production-line stabilization, and hardware-related issues during mass production.

Read and analyze schematics, PCB layouts, component specifications, design documentation, and manufacturing data.

Define test strategies, develop validation plans, execute test procedures, and improve coverage and efficiency.

Collaborate closely with electrical, mechanical, thermal, firmware, software, system, manufacturing, and quality teams throughout the product lifecycle.

Provide technical leadership and hands-on support for critical hardware issues.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab