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We are looking for a Chip Design micro architect for the Networking Silicon group. As a chip micro architect in our Networking business unit, you will join a group of passionate engineers to implement the next generation state-of-the-art BlueField DPU SOC and/or ConnectX NIC that deliver breakthrough networking, security, cloud, AI and storage performance to the AI data centers. As a design micro architect, you will make a real impact in a dynamic, technology-focused AI company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
You will be part of a small and exclusive micro-architecture team and have the opportunity to make a real impact in designing the micro-architecture of the next generation state of the art network card hand in hand with the product architect making sure implementation meets the product goals.
Work closely with architecture and design teams to thoroughly understand system requirements and identify micro-architecture solutions, while weighing trade-offs related to performance, area and power consumption.
Break high-level arch requirements into lower-level design building blocks. Focal point for the design team, reviewing implementation and guiding the team.
Find bottlenecks early in the development cycle using performance analysis and simulations.
Use your understanding of the entire chip and system to identify and debug pre and post silicon full-chip issues.

We are now looking for a HPC Operations Engineer to join our mission and continue improving our HPC infrastructure. A meaningful part of NVIDIAs strength is our unique and advanced development tools and environments that enable our incredible pace of innovation. We are looking for architects to help us evolve the way our private compute cloud is architected and optimized.

What youll be doing:
Troubleshoot incoming support requests in a large-scale HPC environment.
Contribute improvements to existing deployment automation, configuration management, observability, and operational monitoring and day to day operation through automation.
Ensure compute servers are running an accurate Operating System and configuration.
Address Complex Issues: Perform comprehensive issue resolution from bare metal to application level, ensuring system reliability and efficiency.
Collaborate with specialist teams to drive issues to closure.
Collaborate with domain experts to improve how our chip development process utilizes our infrastructure.
Directly contribute to the overall quality and improve time to market for our next generation chips.

We are seeking a passionate QA Engineer to join our FW testing team. This position will be part of our growing team, helping NVIDIA products meet industry-leading benchmarks for efficiency and quality. As a Firmware QA Engineer, you will be immersed in the latest advancements and actively contribute to developing world-class products. Your efforts will directly impact the performance and quality of our offerings, ensuring they consistently meet industry-leading standards.


We are looking for ideal candidates who will actively test industry-leading features in the FW sector, quickly learn new features, conduct both manual and automated testing, and contribute to the development of automation systems.


What you'll be doing:
Review arch design and requirements documents for new features introduced in the Nvlink program.
Join the effort of QA shift left towards simulation for NVL7 generation.
Design, develop, and perform tests for the new features, as part of FW GA or update releases.
Automate newly added tests in the existing automation framework, and add new capabilities and features to the framework.
Report bugs found during execution, assist with reproduction and debugs to understand root cause, verify bug fixes provided by R&D team, and raise if not fixed.
Fully collaborate with different external teams like : :product marketing, R&D, and verification.
Define and build setups topologies for appropriate product coverage.

Job Description
Responsible for the design, development, implementation, and maintenance of automated TEST systems and equipment for company products, from the development stage through production.
Key Responsibilities
* Design and development of TEST systems according to product requirements:
* Define projects, including design approval, budget, and timelines.
* Develop automated tests, hardware, and software, and perform troubleshooting.
* Responsible for documentation, technical instructions, SOW, ATP, and related documents.
* Full responsibility for replication of existing TEST equipment, including procurement, assembly, integration, and testing.
* Provide Technical Support and troubleshooting for production lines and at subcontractors.
* Participate in Design for Testability (DFT) activities throughout the product development process.

Reports to:
ATE team leader

We are looking for a Technical Lead to join our Network System Validation group and lead the validation of advanced networking solutions across complex AI cluster environments. This is a deeply hands-on technical leadership role, combining ownership of the validation roadmap with technical mentoring and engineering excellence. You will develop validation methodologies and automation frameworks, while working hands-on on debugging, performance analysis, and cutting-edge AI networking technologies at scale. Join us to help push our networking technologies to their limits and shape how next-generation AI infrastructure is validated.

What youll be doing:

Review system and product requirements, design validation methodologies, develop and implement comprehensive test plans, functional and performance, for networking technologies in large-scale AI cluster solutions

Develop and maintain benchmarks, automation tools and scripts for test execution, environment setup, log collection, and data analysis.

Lead end-to-end investigation of complex issues by reproducing real-world scenarios, analyzing logs, telemetry, packet captures, and system metrics to identify functional issues and performance bottlenecks, triaging problems across the hardware and software stack, and driving them to root cause and resolution

Read and understand source code (C/C++/Python) to investigate defects, validate fixes, and improve logging, instrumentation, and debugging capabilities

Collaborate deeply with software and hardware development teams to debug networking technologies, including NCCL, RoCE, RDMA, and related software components using targeted experiments and code inspection

Profile and research AI training and inference workloads, correlating application behavior with network and system telemetry to identify scalability and performance limitations

Document findings, communicate technical results, and continuously improve validation methodologies, automation environments, and engineering processes

We are looking for a Senior Software Engineer to join the DOCA SDK Verification team. The DOCA SDK enables developers to rapidly create applications and services on top of our BlueField data processing units (DPUs), leveraging industry-standard APIs. With DOCA, developers can deliver breakthrough networking, security, and storage performance by harnessing the power of our DPUs.

What you will be doing:
As a Senior Software Engineer in the DOCA verification team, you will play a key role in designing and developing the verification infrastructure for the DOCA SDK. This infrastructure is a complex system that executes thousands of tests every night across multiple hardware platforms and configurations. It includes mechanisms for error handling and fault recovery, while test results are stored, analyzed using advanced tools, and presented through live dashboards and reports. Your expertise in building robust and efficient verification systems will be critical to ensuring the reliability and quality of our software.

We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.



What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for a Mechanical Design Engineer to join our mechanical engineering department as a key player in the development of next-generation high-performance interconnects optical solutions for data center servers and storage systems. This key position includes leading the product design throughout all lifecycle stages from inception to Mass production, close interaction with HW, PMC (Product management & configuration), NPI, Thermal, Layout, Quality, and Supply chain teams.


What youll be doing:

Drive all the mechanical design aspects of optical transceivers, including PCB design, opto-mechanical chain and mechanical envelope.

Independently lead product design from concept, through detailed design, and support it during Qualification, NPI and MP stages.

Collaborate in research of ground-breaking technologies, materials, and processes with other groups to bring in creative ideas that solve ever-growing needs.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for our next-generation data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for our next-generation AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of our DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across our next-generation data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

We are looking for a talented Senior Software infrastructure and tools Engineer to join the Data Processing Unit (DPU) SW Group. As a part of the team, you will lead complicated integrations which combining new technologies, automating processes, bringing up full software stacks, developing system scripts for cutting edge networking technologies with the quality requirements of industry-leading customers. You will work closely with our SDK development and gain an understanding of our products and technologies.

What youll be doing:

Crafting efficiency and usability improvements across our proprietary products that will help streamline various release pipelines and processes across us.

Definition and development of SDKs to be used for DPU SW development.

POC of new technologies that require additional development/integration efforts.

Creating and maintaining build system for complex SW products.

Developing tools using our various proprietary and other cutting-edge technologies.

Collaborate with team members, Architects, design, QA teams, and verification.

Our Analog Layout design team is looking for a Senior Analog Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed mixed-signal circuit designs. We have continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our lifes work, to amplify human creativity and intelligence.

What you'll be doing:

Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, SerDes, general I/O's, ESD structures designs in state-of-the-art sub-micron CMOS FinFET technologies using Cadence tools.

You will work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.

Job duties will include floor planning, custom layout and verifying against design rules and schematics, EM/IR analysis.

We are seeking an NPI Engineering Build Manager who is passionate about working on products that enable deep learning. Our team manages the NPI networking supply chain for engineering activities. Activities start from very early engagement with design engineering team and follow through all quick turn NPI builds at the shortest possible cycle time. Our team supports all these engineering quick turn activities by engaging with the engineering team, material suppliers, Operations team, and the PCB manufacturing team. All the parties need to be kept aligned while engineering keeps changing either the material sets or the process.


We are looking for someone can work in a dynamic and fast-changing environment. You are someone who enjoys working on groundbreaking technology and enjoy working with people to take on problems. As a Build Project Manager, you are able to see both the high-level view and be proficient in tracking and following up on detail whether it is an existing product that requires new qualifications or a ground up new product. We will expect you to understand technical detail and be able to translate that into program impact.


What you'll be doing:
Build project's production plan per product's lifecycle, and execute it with NV manufacturers
Communicate with other team members and suppliers to get project details.
Flexibility to adapt to changing requirements, diverse project needs, and tight timelines.
Ability to report on program details in Alignment meetings.
Track and communicate key deliverables, constraints, risks, dependencies and clearly identify critical paths while working with ASIC, product, test, software, board, system engineering and planning teams and other program managers towards a common goal.
Manage cross-functional communications independently, work within a matrixed and publish progress/roadblocks and highlight risks to upper management.
Bring diverse and globally distributed teams together to tackle complex problems and work towards closure.
Lead and attend cross-functional NPI meetings related to your product and highlight key Ops issues while ensuring that the product is ready for production.
Be an active participant in the NPI team by recommending methodology improvements that we can practice as a team.

Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.

What you'll be doing:

As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.

Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.

Optimize package pin out incorporating system level trade-offs of pins assignment.

Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

In close co-operation with the SI/PI/HW design teams and product teams.

Planning, ensuring stakeholder management and leading projects from start to finish.