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we are looking for an expert data engineer to build and evolve the data backbone for our r&d telemetry and performance analytics ecosystem. responsibilities include processing raw, large quantities of data from live systems at the cluster level: hardware, communication units, software, and efficiency indicators. youll be part of a fast paced r&d organization, where system behavior, schemas, and requirements evolve constantly. your mission is to develop flexible, reliable, and scalable data handling pipelines that can adapt to rapid change and deliver clean, trusted data for engineers and researchers.
what youll be doing:
build flexible data ingestion and transformation frameworks that can easily handle evolving schemas and changing data contracts
develop and maintain ETL /elt workflows for refining, enriching, and classifying raw data into analytics-ready form
collaborate with r&d, hardware, DevOps, ml engineers, data scientists and performance analysts to ensure accurate data collection from Embedded systems, firmware, and performance tools
automate schema detection, versioning, and validation to ensure smooth evolution of data structures over time
maintain data quality and reliability standards, including tagging, metadata management, and lineage tracking
enable self-service analytics by providing curated datasets, apis, and databricks notebooks

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

our company is looking for a sw architecture director- a forward-thinking manager to lead the development of ai data centers and networking technologies. in this role, you will be part of a groundbreaking team driving technological innovation! this is an outstanding opportunity to craft the future of ai networking by using innovative technologies to address sophisticated challenges.
what you'll be doing:
identify and evaluate new technologies, innovations, and partner relationships for alignment with our technology roadmap and business value.
lead the development of new networking applications using data plane programming to solve sophisticated networking problems in innovative ways.
engage with customers, publish white papers, write blogs, and present at conferences to share our vision and achievements.
define a strategic vision for our networking in collaboration with adjacent software and hardware architects.

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are looking for a power u-arch senior engineer. our company is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. we are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors and verticals. come join our applied power team to develop state of the art dpu products.
what you'll be doing:
lead a micro-architecture of power features such as: power management, logical power features, etc
work with dpu arch team on power features definition.
understand the workload characteristics for dpu workloads at system scale to drive new hw/sw features.

we are looking for an experienced dft engineer to join an exceptional team of dft experts to develop the next generation dft technologies.
as a dft engineer at the networking group at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

we're looking for a senior software engineer to stand at the forefront of ai innovation in this space. if you're an ai-savvy builder who's ready for the unique and tantalizing challenges of modern vlsi software development, this role is for you!
what you'll be doing:
as our lead AI Engineer, you'll work side-by-side with senior staff to develop systems for a broad range of applications, from data collection and analysis to mcp servers and agentic workflows over our powerful in-house orchestration apis. you'll use nvidia's abundant cloud compute to research and deploy any resources those systems need, take part in critical decisions about which technologies to employ, and assume senior duties in mentoring, code review, and instruction initiatives for the entire team.
innovation and a startup mentality tempered by quality and maintainability standards are in the team's dna. valuable ideas from anyone - junior or senior, newcomer or veteran - are rewarded with the time and creative freedom to bring the vision to life. come build with us!

you'll be responsible for developing architectures, algorithms, models, and methodologies aimed to improve the power consumption of our dpu and nic products.
play a key role in facing these challenges and lead the research of innovative power techniques and power modeling that will drive our solutions to the next level.
take an active part in hw design reviews

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

our company has continuously reinvented itself over two decades. our invention of the gpu in 1999 sparked the growth of the pc gaming market, redefined modern computer graphics, and revolutionized parallel computing. more recently, gpu deep learning ignited modern ai - the next era of computing. nvidia is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. this is our lifes work, to amplify human creativity and intelligence!
we are looking for a senior signal & power integrity engineer. we work closely with our sites in usa and china and have access to extensive knowledge, technologies and tools. yet we are responsible for our own product line of phy ics. taking the products from concepting, through design, implementation, verification and release to customers. if you thrive working with highly skilled people that enjoy reaching challenging goals then nvidia in might be the perfect workplace for you. this is a dynamic team working with state of the art, unique technology. if you are someone that loves a challenge, come join this diverse team and help move the needle!
what you'll be doing:
design high frequencies channels up to 400gb/s per lane for pcbs, packages, connectors and cables.
design layout guidelines for our systems.
simulate passive and active elements in 3d and 2d simulation tools
measure systems in the lab using network analyzer, tdr and scope
master infiniband, ethernet and pci-ex layer 1 specifications and implementation methods
work in an intense environment and control multi-discipline expertise

we are looking for an excellent highly motivated senior SW engineer with experience in Embedded software development to join the software testing team in the data processing unit (dpu) sw group. we are looking for a candidate with the ability to thrive in an environment with complex software and hardware designs, take ownership and lead the sw testing of key components of the dpu. the role includes working closely with hw, fw, and sw teams all over the world, and take our product to next level. 
what youll be doing:
build automated verification environment for high-end hardware and software which is at the forefront of innovation
develop and maintain TEST automation frameworks and scripts using Python
identify, analyze, and report software defects, inconsistencies, and other quality issues
make better product quality by improving tests coverage
take an active part in development, integration and verification with r&d
drive improvements for performance, quality, stability around sw acceleration solutions
stay up to date with industry best practices, new technologies, and emerging trends in software verification

we are looking for an outstanding architect for a senior system architect role for detailed system arch definition in the network adapters hw team. the role includes fine definition of the product hw architecture, taking into consideration cost/performance/power/thermal/security aspects, working tightly with internal teams (marketing/sw/fw/hw) across the corporate as well as lead customers. focus on latest dpu platforms, both stand alone and integrated in larger systems
what youll be doing:
tailor the hw design architecture together with relevant sw/fw architects (dpu management, power management, security solutions etc.)
become a focal point to other system architects at our company for interface definitions and co-design optimizations
lead hw sku optimization with product teams
define dft features with product engineering team
create new cross-org methodologies for better hw-sw co-designs
take an active role in defining system level features in next gen silicon
take an active role in presenting new solutions to lead customers
take an active role in cost optimization solutions

we are seeking a highly motivated  system  architect to join our team of experts and help shape the future of ai & cloud computing. our next-generation bluefield dpus and connectx nics will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to cloud & Storage servers.
what you'll be doing:
define server platform architecture for next generation data center products for ai and cloud, focusing on dense networking solution.
design is highly restricted in space, power and thermals.
define board level and system management architectures for the different platforms
define board level integration and system model for reset, recovery and boot
partner with product, software, design and platform engineering groups for converging plans according to requirements
work with the software team on software and hardware apis
research next generation needs

we are looking for an experienced engineer with a strong background in asic design to join our chip design methodologies team based in tel aviv and yokneam. this team is responsible for establishing asic design methodologies, developing shared code, providing design guidance, and driving the adoption of new technologies. it plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. this role offers an exciting opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.
what you'll be doing:
develop ground-breaking methodologies and innovations to create flawless experience in chip design development
utilize, develop and assimilate ai-based tools and flows
collaborate with chip design stakeholders and peers across the teams to understand existing problems and form the best solutions and methodologies
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our development process
develop training sessions and guide designers with best design practices
develop shared design code and solutions to be widely used by the chip design team