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our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments. This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems. This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products. We are looking for a talented and motivated Masters graduate in Electrical Engineering, with strong interest in Electromagnets and Microwaves, to join our Power Integrity team at our company.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities we are a single SI/EV team is another strong advantage, enabling joint simulation-measurements efforts.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

We are seeking an experienced and driven Quality and Reliability (Q&R) Engineer to own and manage the qualification and long-term reliability of advanced automotive semiconductor products. In this role, you will be responsible for defining, executing, and ensuring product compliance with industry standards (e.g., AEC-Q100, JEDEC, ISO26262), collaborating cross-functionally with design, test, packaging, and manufacturing teams to ensure robust quality performance throughout the product lifecycle.
What your job will look like:
Lead end-to-end quality and reliability activities for new automotive product introductions (NPI), including definition of Q&R plans, stress test strategy, and execution of qualification.
Define and align qualification strategy with AEC-Q100, JEDEC (JESD22), and customer-specific requirements.
Drive reliability risk assessments (FMEA, FMEDA, fault tree analysis) in collaboration with functional safety and design teams.
Manage product qualification timelines, budgets, and documentation, including reliability test reports, risk mitigation plans, and deviation justifications.
Interface with OSATs and test/assembly partners to ensure reliability test execution, including HTOL, ELFR, HAST, PTC, HTSL, and solder joint reliability.
Lead root cause analysis and corrective actions for product or qualification-related failures (FA/8D process).
Act as the Q&R voice in cross-functional reviews (DFX, tape-out, production ramp, and PCN).
Track field returns, drive reliability monitoring, and contribute to continuous improvement activities.
Support audits, customer quality inquiries, and product certifications as needed.

our companys Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles. In our company, Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, and CDPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a relatively small team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our companys EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions, and automation, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

Which department will you join? The SOC verification group owns the important and challenging job of verifying our company's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

We seek a motivated and detail-oriented student to join our SW-ALGO team. In this role, you will be supporting the development and validation of signal processing algorithms and software, working mainly in C++, but also some Matlab and Python. You will collaborate closely with our SW algorithm engineers and system engineers. Our team works on cutting-edge digital communications projects, aiming to develop innovative signal processing algorithms and software.

This exciting part-time opportunity is based in our Haifa office and requires a minimum of two on-site workdays per week. Candidates should have at least four semesters remaining before completing their studies.

Responsibilities:
Assist in the development and testing process of SW algorithms, ensuring accuracy and reliability, including bit-exact testing.
Develop and maintain scripts and automation tools to streamline processes.
Participate in laboratory and experimental activities, including setup and data collection.
Debug complex SW issues through log analysis and on-target testing and find SW solutions.