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we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

we're seeking a visionary Staff Physical STA Expert to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter

Are you looking for a great opportunity to further your career? we are investing in the rapid growth area of Hardware Assisted Verification (HAV).
Our most successful multi-national customers are using our company HAV platforms to verify some of the worlds most advanced System on Chip (SoC) designs. HAV solutions are expanding to a wider audience of smaller companies who are benefiting from early software development and ultra-fast hardware verification through hosted services.
we are looking to hire a Senior Consultant with either Emulation or FPGA prototyping knowledge and experience. This role is ideally suited to someone with a good understanding of HAV platforms who can guide customers through successful HAV deployment and design validation. This is a great opportunity to work with some of the most interesting and innovative people and companies across the semiconductor industry.
The consultant role will be mainly focused on technical services delivery. This could range from platform enablement to methodology guidance. Interactions may be direct with the customer or collaborative through a wider technical team. This position will require a combination of remote, office and onsite working. As a consultant, you will also be expected to uncover opportunities, scope engagements, promote offerings, and grow new business.
Key Responsibilities
A good understanding of HAV platforms and infrastructure (e.g. Strato, Primo or proFPGA enterprise-level systems would be preferable)
A good understanding of HAV compilation and runtime flows (e.g. Veloce or VPS would be preferable)
Practical insights into the application and usage of HAV
Knowledge of design mapping, testbench mapping and pre-silicon validation
Familiarity with HAV debug solutions (probes, waveforms, assertions, coverage, etc.)
Knowledge of virtual TestBench eXpress (TBX) and/or In-Circuit Emulation (ICE) use-cases
Proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification
Strong background in functional verification, RTL synthesis, design partitioning and place-and-route
Conversant with SoC design and architecture concepts.

we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities

Own and develop formal verification environments from scratch through to sign-off
Apply formal verification methodologies and strategies to prove the correctness of intricate designs
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently
Architect and develop generic, common formal functions and properties to be reused across multiple projects

We are looking for a talented Code Generation and Optimization Expert. We are looking for a self-independent engineer to join the team that builds the software infrastructure for accelerating the system in large scale compute environments like data centers and HPC using new CPU core technology. Working on the cutting edge and future ready systems. We work in a development culture that is diverse, flexible and challenging. For persons looking to make an impact and influence the future of computing with personal growth options.

The team is developing core components in the automated optimization process that adapts our unique hardware architecture to run any HPC & AI applications, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.

We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building our next-generation runtime compiler.

Responsibilities
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.

We are looking for a highly experienced a hands-on Compiler Engineer who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
Responsibilities:
Develop our company's compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
Take on complex optimization challenges at the core of our unique compiler, focusing on real-time applications, hybrid quantum/classical algorithms, and parallel processing.
Conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
Hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
Collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.

We are looking for an excellent design engineer to join our team and build our company's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface.