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We are seeking a highly motivated and experienced Sr. Production and Quality Engineer to drive exceptional product quality, patient safety, and field reliability across the Installed Base (IB). This is a key technical role supporting production stability, RMA/DOA investigations, Automated Test Equipment (ATE) performance, and cross-functional quality engineering initiatives in a regulated medical device environment
Key Responsibilities
In this role, you will
Support RMA/DOA processes and continuous reduction of field failures.
Support qualifications and control of ATE testers in production lines.
Support ECO/ECR processes, NPI projects, product updates, and cross-functional engineering changes.
Work closely with R&D, engineering, manufacturing, and operations teams to enhance product quality and resolve technical issues.
Drive continuous improvement initiatives using tools such as Six Sigma, Lean, and Root Cause Analysis (RCA).
Participate in supplier selection and conduct suppliers audits.
Ensure compliance with ISO 13485, FDA 21 CFR 820, MDR, and other applicable medical device regulations.
Maintain and support quality documentation, including CAPA, Non-Conformance Reports (NCRs), and risk management documentation.

Required Project Manager
The Project Manager - Global Lumina Scanner Engineering Department is accountable for leading, coordinating, and executing cross‑functional engineering projects across the full product lifecycle, including NPI, sustaining engineering, production support, test infrastructure, and continuous improvement.
The role ensures alignment between Engineering, Operations, R&D, Quality, and Supply Chain, enabling predictable execution, clear ownership, and end‑to‑end visibility of all engineering initiatives.
Key Responsibilities
Lead and manage multiple engineering projects in parallel across NPI, sustaining, test, electronics, and system engineering.
Build and maintain integrated project plans, milestones, dependencies, and critical paths.
Drive execution through all project phases - definition, planning, execution, validation, and closure.
Coordinate design transfer, manufacturing readiness, validations, and GA milestones.
Own project governance: status reviews, KPIs, risk management, escalation, and decision tracking.
Drive cross‑functional alignment between R&D, Manufacturing, Test, Quality, Supply Chain, IT, and Program Management.
Manage ECO‑driven projects and ensure full impact analysis, execution, and closure.
Support supplier‑related projects including readiness, FAIs, tooling, and ramp‑up activities.
Establish clear ownership, priorities, and communication cadence across all stakeholders.
Provide consolidated, real‑time visibility of project status to management.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

As a Design Verification Engineer, you will be responsible for ensuring "bug-free first silicon" for complex IP and SoC designs. You will drive all phases of pre-silicon verification, from defining methodologies and test plans to RTL freeze and tape-out sign-off. These roles are highly collaborative, requiring close interaction with architecture, design, and software teams across global sites.
Responsibilities
Architect and develop scalable, portable verification environments, including UVM-based testbenches, protocol monitors, agents, and checkers.
Define detailed test and coverage plans based on micro-architecture specifications and extract features for DV attributes.
Create and simulate test scenarios, perform advanced debugging, and conduct end-to-end simulations of data/control paths.
Drive regression and coverage analysis (metric-driven verification) to ensure the highest quality, productivity, and time-to-market.
Partner with architects and designers from the early stages of feature definition to influence IP/SoC specifications.
Apply formal verification, hardware acceleration, and power/performance (NLP) analysis where applicable.

This is a highly visible role where you will own the physical design cycle at the partition, IP, and Chip levels-enabling us to produce fully functional "first silicon" designs. Do you love working on challenges that no one has solved yet? If you are ready to join the world's leading engineers and work with state-of-the-art design flows, come join our group.
Responsibilities
You will be responsible for all phases of pre-silicon development, from initial definition to high-quality tape-out (Netlist to GDSII).
Lead block-level Place & Route (PnR), complex floor-planning, partitioning, and the creation of power domains and grid specifications.
Develop and validate high-performance, low-power clock network guidelines and distribution.
Drive static timing closure (STA), Physical Verification (DRC/LVS), and Electrical/Power analysis (EM, IR-Drop, Xtalk, and Noise).
Participate in establishing CAD and physical design methodologies for "correct-by-construction" designs and assist in flow development for chip integration.
Generate and implement ECOs to fix timing, noise, and EM/IR violations while meeting strict area and power constraints.
Work closely with logic design teams on SoC architecture and HDL (Verilog) to implement timing fixes and design optimizations.