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We are seeking for System Integration Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms. As System Integration Engineer youll join Annapurnas product system team, which develops advanced technologies used across our data centers, supporting services like Nitro and Graviton.
You will take ownership of end-to-end system interfaces (e.g., PCIe, Ethernet, DDR) throughout the product lifecycle, from concept to post-deployment debugging.

Key job responsibilities:
1. Setting interface design strategies.
2. Ensuring optimal design implementation.
3. Driving complex system debugs involving hardware, firmware, and software components.
4. Providing leadership to raise quality standards.

We are seeking for System Integration Engineer to help define, shape, and integrate solutions for the next generation of our cloud platforms. As System Integration Engineer youll join Annapurnas product system team, which develops advanced technologies used across AWS data centers, supporting services like Nitro and Graviton. You will take ownership of end-to-end system interfaces (e.g., PCIe, Ethernet, DDR) throughout the product lifecycle, from concept to post-deployment debugging.

Key job responsibilities:
1. Setting interface design strategies.
2. Ensuring optimal design implementation.
3. Driving complex system debugs involving hardware, firmware, and software components.
4. Providing leadership to raise quality standards.

Our K2Core SW team is looking for a Lead System Test Engineer to define and execute the system validation strategy for the Nitro K2 card. In this technical leadership role, you will own the system-level test definition, drive cross-functional validation efforts, and ensure the end-to-end quality of our Nitro K2 card components deployed across our data centers.

This is a hands-on technical leadership role that requires expertise in embedded systems, hardware/software integration, and test automation at scale. You will work closely with HW, firmware, software, testing and platform teams across us to ensure test coverage, platform integration reliability, and production readiness.

Key job responsibilities:
Define and execute the system-level test and validation strategy for the Nitro K2 card across hardware, firmware, software and platform layers.
Lead the design and development of automated test frameworks to support scalable validation and continuous integration.
Collaborate with hardware, firmware, software, and platform teams to define validation coverage, interfaces, and testability hooks.
Own root cause analysis and debug strategy for complex, cross-subsystem integration issues originating from the production fleet.
Lead and execute hands-on system testing, and participate in the release decision process for production deployment.
Mentor and guide automation engineers, promoting a culture of system-level testing and continuous quality improvement.

Our RADAR VLSI Team is looking for an Embedded SW Engineer for SystemC Modeling that include Performance and Program view Modeling. You will be part of VLSI emulation team , working on current and next-generation designs for next generation sensors.
The SystemC models are fundamental parts of the VLSI chip infrastructure, they are used during HW architecture definition phase and by SW developers for system shift left.
What will your job look like:
You will work on Critical performance analysis and optimizations on the ASIC micro architecture as multi-NOC , DDR and CPU .
You will work on developing SystemC models that describe the RTL models on High level language and enable true system . level shift left for the embedded SW team.
You will have the opportunity to work on state-of-the-art simulation and profiling tools and adopt them to our needs.
You will work closely with HW architects and SW/Algorithms developers.

Required System Level Test Technical Project Manager
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stages and leave your mark, as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like:
Lead the planning, execution, and tracking of System Level Test (SLT) projects across R&D, validation, and production teams.
Work closely with internal design, system, software and hardware teams to define SLT strategy for our SoC products.
Coordinate the development of automated test systems and infrastructure, including test plans, hardware test fixtures, and software tools.
Lead the hardware/software bring-up, enabling and productization activities.
Drive test hardware and software deployment with OSAT vendors to enable large-scale SLT execution and operations.
Enable SLT data collection and analysis and manage production yield excursions.
Drive test time reduction, efficiency improvement, and cost reduction initiatives.
Support RMA analysis with SLT data, SLT-System correlations, and test content enhancements.

Required Senior IC Test Engineer
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like:
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations).
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.

Required Power Integrity \ Signal Integrity Engineer
You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of the company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

Were looking for a Physical Design Expert to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

We are looking for an experienced Hardware Team Lead to manage our Board Design Engineering team within the AV department.
In this critical role, you will drive the development of cutting-edge automotive products by owning the design and delivery of high-performance electronic boards and systems. Your leadership will ensure projects meet the highest standards of quality, performance, and innovation.
What will your job look like?
Lead and Do: Combine strong technical leadership with hands-on hardware engineeringthis role is both strategic and actively involved in execution.
Team Management: Mentor, guide, and grow a high-performing team of hardware engineers, while setting clear technical direction and expectations.
End-to-End Project Ownership: Drive the entire hardware development lifecyclefrom architecture and schematic design to validation and release to mass production.
Design Leadership: Personally contribute and oversee electrical design, schematic reviews, component selection, and layout best practices.
Lab Engagement: Stay closely involved in board bring-up, debugging, and validationworking side by side with engineers to solve tough technical challenges.
Cross-Team Collaboration: Act as a key point of contact across software, mechanical, architecture, and manufacturing teams to ensure seamless product integration.
Customer-Facing Leadership: Represent the hardware team in technical discussions with customers, demonstrating both leadership and in-depth technical knowledge.

We are looking for a Emulation Engineer to join the Radar VLSI team and drive the development of the next generation ASIC Sensors.
What will your job look like:
This role is all about making high-end Emulation environment base on new designs.
Building and integrating complex components, working with cross-functional engineering teams, and making systems that will change the way we drive.
This role requires an engineer who loves challenges and knows how to bring engineering excellence while considering complicated constraints.
You will work with members of a cross-functional talented,
You will lead the Emulation development for the VLSI team.
You will work closely with SW Engineers, Logic Engineers, Verification Engineers, and others.
You will serve as an expert matter for your domain, which has the full responsibility to drive & implement improvements and new ideas.

Our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Required Experienced SoC Verification Engineer
Which department will you join?
The SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Our Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).