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Required Senior Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHSIC Hardware Description Language (VHDL)), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Required Senior DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for application-specific integrated circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, memory built-in self test (MBIST), and automatic test pattern generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required Hardware/Electrical Engineering BS/MS Intern, 2027
Please complete your application before November 13, 2026. We encourage you to apply as early as possible as we review applications on a rolling basis.
About the job
The Cloud and AI Infrastructure team in Israel focuses on building our next-generation systems. The team's work is grounded in creating custom hardware, and as an Intern, you'll get to collaborate with engineers from various parts of the organization to influence the future of Cloud and the AI infrastructure by working on the foundational technology that makes it all possible. This is the hardware that powers everything, from Cloud to our most advanced models like Gemini.
As an Electrical Engineering Intern in the domain of Very Large-Scale Integration (VLSI), you will work on designing, developing and verifying next generation chips for our Cloud Compute Infrastructure. You will have the opportunity to collaborate with engineers from various parts of the organisation to help develop our next generation systems on chip (SOC).
Responsibilities:
Responsibilities and detailed projects will be determined based on your educational background, interest and skills.

We are seeking a Material Planner to join our Supplies Planning Team. This role ensures materials are available on time to support production, maintains optimal inventory levels, and responds to changing production and engineering requirements. The ideal candidate has strong analytical and problem-solving skills, a broad understanding of material planning and logistics processes, and hands-on experience working in a dynamic manufacturing environment. You will work closely with Procurement, Production, Engineering, Logistics, and other cross-functional teams to identify material constraints, resolve shortages, improve planning processes, and ensure production continuity.

Responsibilities:

* Accountable for end-to-end consumables planning and material flow across three production sites in Israel, the Netherlands, and the U.S., from material requirements through production-line availability.
* Manage and optimize material planning processes and information systems, ensuring accurate planning data, material availability, and alignment with production requirements.
* Production control and planning: Monitor production plans, processes, and schedules, and ensure material availability in line with production requirements and BOMs.
* Drive continuous improvement of consumables planning processes by identifying operational challenges and opportunities, prioritizing solutions, and leading implementation.
* Collaborate cross-functionally with Purchasing, Engineering, Production and other operational teams to ensure material availability and resolve supply-related issues.
* Lead cross-functional material forums covering NPI, EOL, Rollovers, inventory & scrap, and material availability, driving alignment, risk mitigation, and timely decision-making
* Manage MRP activities, including material requirements, purchase requisitions, and production requirements, ensuring timely material availability
* Optimize safety stock levels to balance material availability, inventory costs, demand, lead times, and supply risks.
* Manage shelf-life inventory by monitoring expiration dates, applying FEFO (First Expired, First Out) principles, maintaining optimal inventory levels, and proactively minimizing expired materials and waste.


Attributes:

* Ability to work in a rapidly changing and dynamic environment
* Strong organizational skills
* Excellent analytical skills, precision, and attention to detail
* Ability to manage multiple projects and provide support to various departments with diverse requirements and needs

DRS RADA Technologies, a leading defense company developing and manufacturing life-saving radar systems, is looking for a Test Equipment Technician to join our site in Beit She’an. Responsibilities:
* Participate in the assembly and integration of manual and automated test equipment according to engineering designs.
* Perform maintenance of manual and automated test equipment, including troubleshooting, software configuration, and occasional RF calibration.
* Provide support and maintenance for factory test systems, anechoic chambers, ESS (Environmental Stress Screening) equipment, and test & measurement equipment.
* Support ongoing projects and implement new test systems.

Required SoC Test Engineer Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and Outsourced Semiconductor Assembly and Tests (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities
Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, defective parts per million reduction, test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and SLT.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and return merchandise authorization handling.
Drive product leadership for silicon engineering organization from architectural definition to global availability.
Collaborate with cross-functional teams across the globe including ATE and SLT test engineering, quality and reliability, packaging, supplier management and operations to build, deploy, and maintain a high volume manufacturing screening solution.
Manage database integration and advanced usage for wafersort, final test, SLT and burn-in, test program integration, optimization, release to production, binning handling upon need, manufacturing flow definition and implementation, material handling during NPI, skew definition, process optimization with foundry.

Required Package Design/Layout Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Dive into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities. Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on pre-silicon emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues. Collaborate closely with architects, designers, and other teams to drive bug fixes and ensure feature functionality.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage. Mentor and guide junior engineers as the team grows.

Required Senior Emulation Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Required Design AI Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead an edge AI IP design team including definition, implementation and deployment, and define IP development methodologies sharing unified blocks within the IP design team.
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Demonstrate technical involvement throughout the entire Intellectual Property (IP) development cycle, ensuring seamless integration into System-on-Chip (SoC).
Perform RTL development (e.g., coding and debug in SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Collaborate closely with software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.

We are seeking an experienced Embedded Software Engineer to join our R&D team and contribute to the development of next-generation wireless systems.

In this role, you will be involved in the design and development of advanced wireless MESH solutions for our products, as well as cybersecurity capabilities for our wireless platforms, with a growing focus on integrating capabilities developed using LLMs into our products.

This is a hands-on position that combines embedded software development, networking, and AI-oriented innovation.

Reports to: SW team leader in Israel.

Responsibilities
Design and develop advanced wireless MESH communication systems.
Develop high-performance embedded software in C/C++ on Linux-based platforms.
Integrate software within end-to-end systems (HW + SW + Cyber).
Take part in AI LLM -driven feature development and integration (optimization, automation, data analysis).
Collaborate across teams to deliver robust, real-world deployed solutions.

Required Edge-AI Verification Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.

Required Junior RTL Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing, etc. You will develop/define design options for performance, power and area.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the IP microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog).
Conduct function/performance simulation debug and Lint/CDC/FV/UPF checks.
Engage in synthesis, timing/power closure, and ASIC silicon bring-up.
Contribute to verification test plan and coverage analysis of block and SoC-level.