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The System & Network Architecture Team within Computing Network Innovation Lab is responsible for next generation computing network architecture research, ranging from network architecture evolution technology to large scale network technology (e.g. Ethernet/IB/RoCE), bus network technology (PCIE/CXL), chiplet interconnect technology and strategic technology planning
DESCRIPTION:
With the explosive growth of AI technologies and the Internet industry, data centers have become digital hubs and infrastructures of the Internet industry in the digital economy era. Computing networks, as core components of data centers, have features such as topology, scalability, throughput, reliability, and latency that directly affect data center functionality and performance. The computing cluster networking lab explores architecture and technological innovation for meeting the challenges of future large-scale AI & HPC data centers. .. The labs mission is to lead our company to achieve differentiated competitiveness in high-performance computing cluster network infrastructure, and to support Huawei's industry-leading computing cluster.
Position Overview
In this role, you will be responsible for several teams of architects, engineers and software developers, all working together to conduct state-of-the-art R&D in system and network architecture. As the group lead, you will guide and mentor the individual team leads, and also conduct hands-on work leading architecture, technology innovation and technical planning and of high-performance computing cluster network, which oriented at AI, HPC, and big data.
Responsibilities
You will perform a wide range of duties including:
Architecture Innovation:
Deeply analyzing the advantages and disadvantages of mainstream network systems, to find opportunities for network architecture innovation;
Insight into the technology developing trend of the high-performance computing network field, and leading the corresponding technology planning.
Exploring new architectures of high-performance computing network systems and efficiently integrating communication library, topology, and network protocol to solve performance bottlenecks.
Technical breakthroughs in networking and cluster routing algorithm：
Analyzes computing cluster network performance and leads the development of computing cluster network technologies
Research and optimize the heterogeneous interconnection topology of key computing chips to continuously improve the key competitiveness of Huawei computing heterogeneous chipsets
Responsible for the research of data center network technologies, and guide network topology design and routing algorithm development
Group leadership:
Lead the development of a comprehensive system architecture for AI Fabric and HPC Fabric solutions
Manage and mentor highly skilled team leaders, to ensure that the group operates together in pursuit of common goal
Foster a collaborative and innovative work environment
Provide technical guidance and support to team members
Collaborate closely with cross-functional teams internationally, including hardware,
software, and ucode design teams, to ensure alignment of architectural decisions with
product and platform common objectives
Initiate and supervise collaborations with top academic researchers in Israel and abroad
Stay up to date with emerging technologies and industry trends in AI, HPC and big data industries.

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage and networking at large-scale. We aim to drive innovations and deliver software defined infrastructure and algorithms to HPC, AI/ML, and Big Data applications.
We are looking for outstanding candidates with hands-on experience in development and optimization of AI frameworks. If you are a team player with excellent communication skills and motivation to revolutionize application performance, youre welcome on board!
What will you be doing?
Work as part of an innovative research team to analyze, develop, test and deploy improvements that enhance Huaweis distributed AI framework.
Develop optimizations that leverage hardware accelerator capabilities, minimize communication overhead and improve training/inference throughput
Push the boundaries of the state of the art in LLM performance and efficiency, including model compression and quantization
Analyze, profile and optimize the latest LLM AI algorithms, and implement as production-quality software libraries for latency-critical use-cases on next-generation hardware.
Work in a distributed computing environment to optimize for both scale-up (multi-device) and scale-out (multi-node) systems
Utilize advanced concepts such as Uncertainty Quantification, Mixed Precision Computing and Model Sparsity to improve performance and enable training of very large AI models
Collaborate with partners from top universities, and open-source communities to conduct state-of-the-art research.

our company, Huaweis Tel Aviv Research and Innovation Center, is looking for an experienced hands-on software architect with expertise in Cloud, AI, and Distributed Systems to join our AI-accelerated Cloud Storage group. The team designs and develops cutting-edge cloud technologies that power next-generation AI applications, optimizing performance, scalability, and efficiency.
The role involves both high-level system understanding and low-level grasp of the connection between storage and AI, to push the boundaries of cloud infrastructure for AI workloads. If you want to be part of something bigger, if you are a team player with excellent communication skills and the motivation to revolutionize AI-driven cloud technologies, youre welcome on board!
What Will You Be Doing?
Research, design, and innovate cloud-based AI acceleration technologies
Analyze AI application performance, identify bottlenecks, and optimize decision-making mechanisms
Collaborate with other engineers to develop AI optimizations, Storage backend and related POCs.
Investigate global trends in AI infrastructure and cloud computing to shape long-term architecture
Collaborate with global teams on next-generation cloud solutions for AI.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Will drive the implementation of autonomous core power management for best performance and power efficacy.
The Power expert will take charge in understanding business-units (customers) needs, and translate them to CPU core solution.
This expert will utilize his power management experience to deliver world-class power efficient HW-SW solutions for Huawei products.
Responsibilities
Responsible for bringing Huawei CPU to a leading position in Performance-Power efficiency.

Please submit your resume to be added to our student job database, and once a student position opens, we will be able to contact you if it's a match.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.