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We are looking for a skilled and motivated Embedded SW Integration Team Lead for the Platform OS Department to manage the daily integration of the OS deliveries into our SW stack. The Platform OS team is leading a global effort of making the Linux OS as the Automotive Safety OS that will fuel the Autonomous Vehicle and the whole automotive industry. Youll lead a fast-paced, hands-on and dynamic team of integration and automation engineers, contributing to the overall qualification and integration effort while collaborating with other teams across the organization.
What will your job look like:
Lead and mentor a team of 4-6 SW Integration and Automation engineers
Manage the daily integration of the aggregated delivery of all OS teams upstream into our SW stack.
Daily tracking of changes coming from OS development teams and controlling their integration order, priorities, test coverage and conflicts.
Managing a daily integration forum to track nightly tests reports, triaging new issues found and assigning them to development teams.
System level understanding of the OS features and tracking the test coverage developed by the OS developers.
Tracking the utilization, health and allocation of the HW resources in the farm.
Balancing test coverage to HW availability through tracking CI load.
Acting as a PoC for all OS integration issues. Both within the OS teams and externally.
Tracking bug escapes and their mitigation in the OS test coverage.

Our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Required Experienced SoC Verification Engineer
Which department will you join?
The SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Our Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Required Experienced RFIC/Analog CAD Engineer
The RFIC/Analog design groups in our Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization.
To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement.
We're looking for an Experienced CAD or Design Automation Engineer to develop our RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations

Required Experienced Physical Design Engineer
The EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence.
We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Required Experienced Logic Design Engineer
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

We are looking for a Emulation Engineer to join the Radar VLSI team and drive the development of the next generation ASIC Sensors.
What will your job look like:
This role is all about making high-end Emulation environment base on new designs.
Building and integrating complex components, working with cross-functional engineering teams, and making systems that will change the way we drive.
This role requires an engineer who loves challenges and knows how to bring engineering excellence while considering complicated constraints.
You will work with members of a cross-functional talented,
You will lead the Emulation development for the VLSI team.
You will work closely with SW Engineers, Logic Engineers, Verification Engineers, and others.
You will serve as an expert matter for your domain, which has the full responsibility to drive & implement improvements and new ideas.

Our Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles.
Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, and CDPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a relatively small team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions, and automation, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

A Huawei Research Center in Israel focusing on research and development of innovative concepts and future technologies in the fields of Communication, Artificial Intelligence and others. The technical teams include lead industry experts in various fields.
Artificial Intelligence group at is responsible for conducting state of the art research and algorithms development in the areas of Machine/Deep Learning (ML/DL), Computer Vision (CV), Optimization, and Information Theory.

We are looking for outstanding researchers with PhD in Electrical Engineering, Computer Science, or Mathematics, with a background in (either) ML, CV, Robotics, and desirably, hands on Deep Learning experience. The successful candidate will join a team of scientists and participate in rewarding scientific research to develop novel theoretical methods and algorithms, and to publish it in scientific journals and conference proceedings.
The position involves generation of novel ideas in the above fields, invention and design of new methods to advance state-of-art. Proven academic record is a must.

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage and networking at large-scale. We aim to drive innovations and deliver software defined infrastructure and algorithms to HPC and AI/ML in distributed run environment.
We are looking for outstanding candidates with hands-on experience in software development. If you are a team player with excellent communication skills and motivation to investigate state-of-the-art directions and revolutionize application performance, youre welcome on board!
Responsibilities
Envision, design and develop new features in all layers of the HPC / AI stack, from the application level, through the programming model (e.g. OpenMP, MPI) and down to the supporting libraries/middleware
Research, design and implement features for HPC / AI applications using parallel programming models (e.g. OpenMP, MPI), accelerators offloading and memory tiers.
Contribute to open-source scientific computing, networking and I/O libraries
Research, design and assist in developing hardware offloads for features relevant for scientific, deep learning, and data-intensive workloads.

we make lifes experiences unforgettable. We believe there is extraordinary power in the self-expression. Thats why our family of brands helps customers create products and capture moments that reflect who they uniquely are.

Were looking for a Principal Android Engineer to help shape the future of our Android mobile platform. In this role, youll drive the development of innovative mobile experiences used by tens of millions of people. Youll collaborate with a talented cross functional team to help evolve our app while helping to maintain the highest standards of quality, performance, and user experience.
What You'll Do Here
Champion a culture of technical excellence through thoughtful code reviews, mentorship, and continuous improvement
Drive improvements in app performance, reliability, maintainability, and engineering best practices
Lead design, architecture, and development of high-impact Android features across family of apps
Contribute to the evolution of our mobile platform, architecture, and tooling, with a focus on scalability and reusability
Collaborate closely with product managers, UX designers, and back-end teams to craft experiences that delight users

we make lifes experiences unforgettable. We believe there is extraordinary power in the self-expression. Thats why our family of brands helps customers create products and capture moments that reflect who they uniquely are.

We are looking for a hands-on and visionary Principal Tech Lead (Principal Software Engineer) for the Personalization & Martech group to guide our architecture and engineering efforts as we evolve into the next generation of our platform. In this highly visible role, youll lead technical direction across projects, mentor developers, and help modernize both our stack and processes. You'll collaborate closely with product, analytics, and marketing to deliver scalable and impactful systems that power personalized journeys, customer engagement and campaign automation.

Responsibilities:
Drive technical leadership across Personalization and Martech teams, setting architectural standards and best practices
Lead the migration from legacy monoliths to micro-services and micro-frontends
Develop tools and integrations using React, TypeScript, Node.js, and Python
Architect cloud-native systems using AWS Lambda, API Gateway, CloudFront, DynamoDB, and S3
Design scalable, secure, and observable APIs and event-driven systems using SNS, SQS, Kafka, and Kinesis
Partner with Marketing and Product to build personalized customer experiences, experimentation frameworks, and campaign infrastructure
Support and evolve legacy systems to maintain business continuity during platform transition
Set and uphold high standards for code quality, system design, and documentation
Mentor engineers and guide technical decision-making across multiple squads
Champion innovation through the introduction of LLM-powered automation, internal tools, and AI-driven optimizations