דרושים » חשמל ואלקטרוניקה » Experienced SoC Design Engineer

Our Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Testing (DFT) Engineer you will be responsible for defining, implementing and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for a CPU. You will design, insert and verify the DFT logic.You will prepare for post silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality and enhancing yield.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the DFT Senior Engineer, you will play a crucial role in DFT Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project lifecycle, and providing sign-off DFT to tapeout.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project - planning, execution, tracking, quality, and signoff.

About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Frontend Design Engineer, you will take part in central processing unit (CPU) development, a complex and critical blocks of our companys sever System on a Chip (SoC). You will be responsible for microarchitecture and RTL design and implementation of core technology as part of our companys data center SoC products. You'll collaborate closely with architecture, verification, and physical design engineers, creating micro-architectural definitions with RTL coding and running block level simulations.
The ML, Systems & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companys, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC-level verification.

Required Experienced SoC Verification Engineer
Which department will you join?
The SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Required Senior IC Test Engineer
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like:
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations).
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use Application-Specific Integrated Circuit (ASIC) design to be part of a team that creates the System on a Chip (SoC) design cycle from start to finish. You will collaborate with design and verification engineers in projects, creating architecture definitions with Register-Transfer Level (RTL) coding, and running block level simulations. You will contribute in ASIC designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and more to specify and deliver high quality SoC/RTL. You will also solve technical problems with micro-architecture and solutions, and evaluate design options with performance, power, and area.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

About the job
our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
As a Chip Infrastructure Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on infrastructure that enables design and verification teams to produce the chips that power our company's computing needs. You'll be part of the chip infrastructure team responsible for compute, storage, common chip design components, and front-end tool flows.
In this role, you will work with architects, logic designers, and verification engineers to develop flows to build and verify SoC chip designs. Youll also work closely with software, physical design, silicon bring-up and validation teams to enable a successful software integration, implementation, silicon bringup and deliver quality silicon.
The ML, Systems, & Cloud AI (MSCA) organization at our company's designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company's services (Search, YouTube, etc.) and our companys Cloud. Our end users are our companyrs, Cloud customers and the billions of people who use our company's services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company's Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Work with partner teams to provide the compute, storage and methodology needs of the chip design, verification and physical design teams.
Collaborate with Application-Specific Integrated Circuit (ASIC) teams to implement tools and methodologies.
Design and implement CAD tools, solutions and methodologies for ASIC development.
Extend the capabilities of third-party tools through their dedicated APIs.
Provide documentation, training, and support to increase end user productivity.