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we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are looking for an experienced Senior Signal Integrity Engineer to join our Hardware Engineering team. This role focuses on ensuring optimal signal integrity for high-speed interfaces, including Ethernet, PCIe, DDR5, and other next-generation technologies. As part of the team, you will be responsible for performing signal integrity analysis, developing signal integrity models, and ensuring electrical compliance for high-speed SERDES I/Os.
Responsibilities:
Conduct signal integrity analysis and simulations for high-speed interfaces such as 112Gbps Ethernet, PCIe Gen5, and DDR5 interfaces.
Develop and implement signal integrity guidelines for PCB design, ensuring high-performance and low-loss signal paths.
Analyze and resolve signal integrity issues related to high-speed interfaces, including reflection, crosstalk, and power delivery network (PDN) issues.
Collaborate with PCB layout engineers to optimize design for signal integrity, ensuring compliance with electrical standards and high-speed design best practices.
Perform time-domain and frequency-domain analysis, including loss, jitter, and eye-diagram analysis.
Utilize EDA tools such as Ansys SIWAVE, HFSS, or similar for simulation and validation of signal integrity designs.
Work closely with cross-functional teams to integrate signal integrity considerations into the overall hardware design process.
Develop behavioural models based on measured signal integrity data to inform future design and simulation work.
Conduct pre- and post-layout simulations and measurements for high-speed signal interfaces.

we are hiring a senior physical Verification engineer to lead signoff-quality verification for advanced silicon programs. you will drive physical verification strategy and closure for complex designs, working across implementation, methodology, and signoff teams to achieve tapeout readiness. the role requires strong technical ownership, structured debug, and the ability to scale best practices across multiple programs. this is a great match for an engineer who wants to combine technical depth with broad project impact.
what you'll be doing:
own physical verification closure for major blocks or full-chip designs through tapeout.
lead debugging of complex drc, lvs, and reliability-related issues and drive high-quality resolution.
define verification check plans, signoff criteria, and closure priorities with cross-functional teams.
partner with physical design, custom design, and cad teams to improve quality and turnaround.
drive automation, methodology improvements, and best practices for scalable pv execution.
review results, coach team members, and help reduce repeated classes of violations.
we are committed to fostering a diverse work environment and proud to be an equal opportunity employer. as we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. we will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. please contact us to request accommodation.

job overview:
join our gpu hardware verification team in raanana, israel, and help shape the future of the world's most widely deployed gpu architecture - mali. as a staff hardware Verification engineer, you will play a key technical role in verifying advanced gpu components and subsystems, working alongside architects, designers and Verification engineers to deliver high-quality, industry-leading graphics technology. you'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
responsibilities:
develop and execute verification plans for advanced gpu components and subsystems.
develop and maintain ai tools, agents, and skills to support our engineering teams and workflows.
build, maintain and enhance robust verification environments using systemverilog and uvm.
apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
debug complex functional issues and work closely with design and architecture teams to identify and resolve root causes.
contribute to block-level and system -level verification, including environment integration and regression analysis.
improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
participate in verification reviews and support verification sign-off activities.
share technical knowledge and collaborate with colleagues across the wider gpu engineering organisation.

are you ready to make a significant impact by tackling sw verification challenges? our networking is seeking an exceptional candidate to work with world-class technologies in the domains of high-speed communication and virtualization for our most advanced markets and customers. our products encompass ethernet and infiniband protocols, delivering a wide range of cutting-edge networking, Storage, and security services for cloud, complex compute, and ai workloads. as a software Verification engineer, you will play a crucial role in ensuring on-time and high-quality releases.
what you'll be doing:
take an active part in development, integration, and verification with r&d
develop and maintain TEST automation frameworks and scripts using Python
identify, analyze, and report software defects, inconsistencies, and other quality issues
drive design verification flows and methodologies improvements
perform functional, integration, and regression of software applications and networking protocols
work with planning and tracking systems to manage the release progress and build release indicators
participate in code reviews, provide feedback, and suggest improvements to enhance the quality and maintainability of the software
continuously monitor and evaluate the effectiveness of TEST processes and methodologies, recommending improvements as necessary
stay up to date with industry best practices, new technologies, and emerging trends in software verification and QA
make better product quality by improving TEST coverage

we are seeking a highly skilled senior performance engineer to join our performance and r&d organizations. in this role, you will help build and evolve systems that support performance analysis, telemetry, and optimization for large-scale gpu- and cpu-based clusters used in ai and high-performance computing environments. you will work closely with hardware, networking, firmware, and software teams to collect, analyze, and interpret performance data from live systems. this is a fast-paced r&d environment where system behavior and requirements evolve rapidly, requiring adaptable engineering solutions and strong analytical thinking.
what you'll be doing:
profile, benchmark, and analyze ai and hpc workloads on gpu and cpu clusters
explore performance characteristics of high-performance networking and collective communications (e.g., nccl, rdma, mpi, roce)
identify performance bottlenecks across networking, compute, memory, and system architecture
develop and enhance performance analysis, benchmarking, and diagnostic tools
define performance TEST plans and establish expectations for new technologies and platforms
collaborate across hardware, firmware, networking, systems, and software teams to provide actionable performance insights
support telemetry collection and data refinement efforts to enable accurate performance analysis
maintain high standards for data quality, reproducibility, and traceability of performance results

we are looking for a program manager with technical skills for hw r&d organization, responsible for programs and project on various network products. the pm will drive execution and scheduling of hw projects while aligning with corporate priorities and constraints.
what you'll be doing:
responsibility to coordinate between all project stakeholders such as marketing, engineering teams, operations etc. from initial requirements definition through delivery.
work with project managers and engineers to ensure consistency with company strategy, commitments, and goals.
responsibility for developing and implementing hw methodologies and project management processes and tools.

our chip design group is looking for best-in-class Verification engineers to join our outstanding silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovative chips, and enjoy working in a meaningful, growing, and highly professional environment where you make a huge impact in a technology-focused company.
what you'll be doing:
verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to performance.
daily work involves acquaintance with all aspects of chip development: design, micro- architecture, firmware, production, and verification.
engage in cutting-edge pcie generation working on latest pcie gen7.

what if your Python automation caught a critical asic bug before the physical silicon was even manufactured? our simulation platforms make that happen every release cycle! we are the system ethernet QA team at our r&d center, responsible for the testing and qualification of virtual networking silicon (simx) and software-from l2 forwarding and l3 routing to overlays, qos, and security. with simx, developers and QA engineers get hardware-free, early access to the asic for better debugging.
we are looking for a senior QA software engineer who combines network protocol expertise with strong Python automation skills. does debugging a bgp evpn route leak excite you as much as refactoring a TEST framework? then we should talk!
what you'll be doing:
we don't just complete checklists; we collaborate closely with r&d to lead the quality of new features from design to deployment. in this role, we:
review architectural designs and requirements for new features introduced to the product
drive the design, development, and execution of tests across functional, performance, and security scopes as part of sw ga and update releases
develop Python automation suites built on clean oop principles
chase down defects and validate fixes until we fully resolve the root cause
leverage the simx platform to validate code and debug the asic long before hardware arrives

we have been redefining computer graphics, pc gaming, and accelerated computing for more than 25 years. it's an outstanding legacy of innovation that's motivated by phenomenal technology-and amazing people.as a member of our team, you'll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. join the team and discover how you can build a lasting impact on the world.we are looking for a hardware architecture engineer to join the hardware team! hardware team responsible for full execution of systems, adapters and interconnect for ai cluster deployments.
what you'll be doing:
lead hardware next generation end-to-end definition and architecture (switch,interconnect, adapter)
define form factor selection; si, power and thermal consideration, and channel optimization (mech/thermal/cluster layout)
align hardware systems and chip design teams toward unified definition
combine understanding of hardware end-to-end in parallel with software aspects
the position requires working closely with different engineering and operations teams
a hands on enginer who is familiar with new technologies and can take a task from scratch to completion with ease!