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Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud. Our end users are Googlers, Cloud customers and the billions of people who use our services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Senior SOC Performance Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Validate performance and power models from the architecture team and lab measurements against established goals, exercise open source benchmarks, analyze the results, and identify optimization opportunities.
Design and build tests to verify SoC design meets targets, and implement advanced technologies for running "benchmark representations" on pre-silicon environments.
Analyze problems to identify core design weaknesses, and drive resolution of performance issues in both pre- and post-silicon environments.
Collaborate closely with design, validation, and architecture teams to ensure hardware and software designs interface correctly and deliver products.
Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making, and drive efforts to productize features that improve performance and power characteristics.

> Design and development of complex anlog & digital boards for Motion Control applications.
> Participate in the architecture design of future applications and products. > Support existing designs, implement changes and reliability. improvement enhancements, TEST and validate new designs.
Primary Duties and Responsibilities:
> Design and develop complex boards.
> Define Requirements, engineering specs and Validation documents.
> Select major components, lead layout and placement using contractors. > Perform Bring-Up tasks, validate design, support transition to manufacturing, support the boards in their life cycle.

we are looking for a senior VLSI Design Engineer highly experienced in developing designs for complex SoC devices, from arch/uarch definition to coding and verification. In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.
If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.
Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

we are looking for an experienced Product Line Manager (PLM) for the IoT portfolio to lead product-line planning and execution across the full lifecycle of IoT solutions. This role will own roadmap definition, market and customer requirement analysis, product specification, launch readiness, and ongoing business growth for a portfolio that includes IoT gateways, cellular routers, industrial switches, and related services and platforms. The role works cross-functionally with R&D, solution management, business development, sales, marketing, operations, global services, and partners and OEMs to turn IoT value proposition into market wins.
Location: Ramat Hachayal, Tel Aviv. Hybrid option once a week.
Responsibilities
Own the IoT product line lifecycle from strategic planning through execution, launch, and lifecycle management.
Define and maintain the portfolio roadmap, balancing short-term customer needs with long-term strategic priorities.
Translate market needs, customer use cases, and competitive input into product requirements, business cases, pricing and COGS targets, and time-to-market plans.
Lead PLM-owned stages in the feature and release lifecycle, including feature requests, high-level business case creation, GTM readiness, and go / no-go decisions.
Define product functionality through technical specifications and use cases, and work closely with R&D to ensure high-quality end-to-end delivery.
Drive commercialization of IoT portfolio, including offers around secure and resilient SCADA transport, smart IoT solutions, and industrial and utility connectivity use cases.
Work with marketing and product marketing on positioning, launches, presentations, data sheets, webinars, GTM toolkits, and sales enablement content.
Partner with sales and account teams to support customer opportunities, RFIs / RFPs, partner discussions, and strategic deals.
Manage and prioritize initiatives tied to IoT differentiation, including security-by-design, certifications, protocol conversion, edge intelligence, and resilient communications.
Monitor market trends, competitor activity, and adjacent technologies such as private LTE / 5G, edge computing, AI / ML integration, and industrial IoT applications to shape roadmap decisions.
Where relevant, manage partners and OEM relationships, including specifications, commercial alignment, customizations, and sales support.

We are looking for a Senior PCB Design layout Engineer to join our Hardware engineering team at the Autonomous Vehicle Platform department as a key player in the development of next-generation ECU (electrical control unit) for autonomous vehicles.
What will your job look like?
Working closely with hardware and mechanical design engineers, you'll perform PCB layout our ECUs and other products.
Complete development of CAD layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
Be responsible for the design releases required generation of artwork files, ODB++, FAB drawings, ICT report, and electronic PCB documentation.
Your designs will need to follow IPC class 3 , signal and power integrity constraints, EMI/RFI control and automotive regulations..

we are looking for a Experienced Verification Team Leader.
Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.
Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station
Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

Required Senior IC Test Engineer
Haifa
Full time
We are the Production Test team - responsible for the definition, development, and deployment of production test operations for the worlds most advanced SoCs for ADAS and self-driving vehicles.
This is your opportunity to join a team during its initial forming stage and leave your mark as we assume full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products.
What will your job look like?
Work closely with the design teams from early stages of the design process to review DFX architecture and define test requirements.
Define test methodologies and generate test content for high-speed interfaces of embedded IP blocks (LPDDR4/5, PCIe Gen4/5, D/C/MPHY).
Test program coding, pattern conversion and pre-Si validation (virtual test simulations)
Support Load Board and Probe Card design activities.
Lead post-Si test program debug activities to enable delivery of samples to internal and external customers.
Test program characterization and tuning to enhance test program quality to meet automotive standards.
Support Quality & Reliability team to enable effective and timely qual plan execution.
Lead test deployment activities with tier-one Foundry and OSAT vendors to enable large-scale Wafer-Sort and Final-Test operations.