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we are looking for a chip design micro architect for the networking silicon group.as a chip micro architect at our company networking business unit, you will join a group of passionate engineers to implement the next generation state-of-the-art bluefield dpu SOC and/or connectx nic that deliver breakthrough networking, security, cloud, ai and Storage performance to the ai data centers. as a design micro architect, you will make a real impact in a dynamic, technology-focused ai company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
you will be part of a small and exclusive micro-architecture team and have the opportunity to make a real impact in designing the micro-architecture of the next generation state of the art network card hand in hand with the product architect making sure implementation meets the product goals.
work closely with architecture and design teams to thoroughly understand system requirements and identify micro-architecture solutions, while weighing trade-offs related to performance, area and power consumption
break high-level arch requirements into lower-level design building blocks. focal point for the design team, reviewing implementation and guiding the team.
find bottlenecks early in the development cycle using performance analysis and simulations
use your understanding of the entire chip and system to identify and debug pre and post silicon full-chip issues

as our company, we see problems that others have never encountered. to solve them, we use capabilities and access to technology that few people possess. our group leads, invents, evangelizes, creates architecture, and educates on applying these novel technologies. we are currently seeking a hard-working senior system and hardware timesync architect who flourishes with these types of challenges to join our time synchronization architecture team.
in this role, you will be exposed to the newest technologies and will help define how our gpus, cpus, and networking devices use timing to power extraordinary products and applications. specifically, you will focus on next-generation innovative, scalable, and power-efficient timesync solutions. by working across hardware and software stacks, you will support sophisticated ai acceleration and drive industry-wide standardization. if you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.
what youll be doing:
master our time synchronization technology
define of hardware and system architectures
research and evaluate algorithms currently used in related applications
develop complex proof-of-concepts to demonstrate ideas
collaborate with software architects to define new features and robust sw-hw interfaces for diverse networking use cases.
drive standardization and interoperability to support broad industry adoption.

at our company, we are building the ai factories that power the future of human intelligence! as we scale from thousands to millions of gpus, the "pipes" that connect them have become the most critical bottleneck in modern computing. this is where you come in! we are looking for a visionary senior system architect to lead the charge in defining how we move data at speeds the world has never seen. we want to bridge the gap between silicon and the rack, ensuring our nvlink and infiniband fabrics remain the gold standard for performance. this is a chance to join a team where we don't just follow industry standards-we set them!
you will work at the intersection of signal integrity (si), mechanical engineering, and system protocol design to ensure that our nvlink and infiniband/ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
what youll be doing:
architectural definition: lead the end-to-end definition of high-speed interconnect systems for next-gen ai platforms (e.g., rubin and beyond), focusing on 224g/448g pam4 lanes and beyond.
technology roadmap: evaluate and select pioneering technologies such as co-packaged optics ( CPO ), silicon photonics, and advanced osfp/qsfp-dd form factors.
system co-design: collaborate with asic, thermal, and pcb teams to optimize the "silicon-to-connector" path, minimizing insertion loss and improving signal integrity.
standardization leadership: represent our in industry standards bodies (e.g., ieee 802.3, ocp, msa) to influence the future of high-speed connector and cable specifications.
vendor ecosystem: work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
performance modeling: conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (copper vs. optical).

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

our company networking is a leading supplier of end-to-end ethernet and nvlink intelligent interconnect solutions and services for servers, Storage, and hyper-converged infrastructure. the company hw microarchitecture group is looking for an extraordinary solution architect to participate in helping our customers to get the maximum performance from our network products. the successful candidate will show strong background in chip design (arch, microarch, design, dv), excellent system view, ability to work independently, good communication and motivation to solve sophisticated problems.
 
what youll be doing:
help customers get the best performance from our products.
debug sophisticated customers issues.
come up with solutions for current and future products.
work with teams and customers from around the world.
partner closely with our field engineers and architecture.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.

our company networking is a world-leader in building the most powerful supercomputers in the world which drive the ai and hpc industry. these rely on high performant network asics which connect gpus at scale for efficient data transfer and compute.
we are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. the role is cross-disciplinary, collaborating with hardware and software teams across the wider company.
you will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.
what you'll be doing:
develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for our next generation of switches.
learn and understand the switch asic across all performance related aspects
focus on switch hardware modeling.
analyze and model the communication patterns of key DL, gai inference and training applications.
explore innovative ideas to improve and optimize our chip systems performance.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.

we are looking for an outstanding architect for a senior system architect role for detailed system arch definition in the network adapters hw team. the role includes fine definition of the product hw architecture, taking into consideration cost/performance/power/thermal/security aspects, working tightly with internal teams (marketing/sw/fw/hw) across the corporate as well as lead customers. focus on latest dpu platforms, both stand alone and integrated in larger systems
what youll be doing:
tailor the hw design architecture together with relevant sw/fw architects (dpu management, power management, security solutions etc.)
become a focal point to other system architects at our company for interface definitions and co-design optimizations
lead hw sku optimization with product teams
define dft features with product engineering team
create new cross-org methodologies for better hw-sw co-designs
take an active role in defining system level features in next gen silicon
take an active role in presenting new solutions to lead customers
take an active role in cost optimization solutions

we are seeking a highly motivated  system  architect to join our team of experts and help shape the future of ai & cloud computing. our next-generation bluefield dpus and connectx nics will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to cloud & Storage servers.
what you'll be doing:
define server platform architecture for next generation data center products for ai and cloud, focusing on dense networking solution.
design is highly restricted in space, power and thermals.
define board level and system management architectures for the different platforms
define board level integration and system model for reset, recovery and boot
partner with product, software, design and platform engineering groups for converging plans according to requirements
work with the software team on software and hardware apis
research next generation needs

description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
at the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
join our cutting-edge hardware development team as micro-architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
what you'll do:
define and develop micro-architecture for complex logic blocks - from concept through high-quality rtl implementation
collaborate closely with architecture, verification, design and software design teams
write clear and detailed design specifications and drive architectural trade-off analysis
optimize for performance and area
contribute to innovation, methodology improvements, and technical leadership within the team.