דרושים » חשמל ואלקטרוניקה » networking architect

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology

Define of hardware and system architectures

Research and evaluate algorithms currently used in related applications

Develop complex proof-of-concepts to demonstrate ideas

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

as our company, we see problems that others have never encountered. to solve them, we use capabilities and access to technology that few people possess. our group leads, invents, evangelizes, creates architecture, and educates on applying these novel technologies. we are currently seeking a hard-working senior system and hardware timesync architect who flourishes with these types of challenges to join our time synchronization architecture team.
in this role, you will be exposed to the newest technologies and will help define how our gpus, cpus, and networking devices use timing to power extraordinary products and applications. specifically, you will focus on next-generation innovative, scalable, and power-efficient timesync solutions. by working across hardware and software stacks, you will support sophisticated ai acceleration and drive industry-wide standardization. if you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.
what youll be doing:
master our time synchronization technology
define of hardware and system architectures
research and evaluate algorithms currently used in related applications
develop complex proof-of-concepts to demonstrate ideas
collaborate with software architects to define new features and robust sw-hw interfaces for diverse networking use cases.
drive standardization and interoperability to support broad industry adoption.

our networking division is a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, optical transceivers, cables, and software to support networking technologies. our products optimize data centre performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors including high performance computing, enterprise, data centres, cloud computing. we are constantly reinventing ourselves to stay ahead of the market and bring ground-breaking products and services to the industry by using novel technologies. our products are focused on delivering the most optimized power - performance communication solutions for industries like ai, ml, cloud, media and entertainment. 
we are seeking experienced electrical engineers with a passion for system -level thinking and innovation in high-performance optical switch development. this role offers a unique opportunity to shape and deliver next-generation products that push the boundaries of high-speed optical communication.
what youll be doing:
leading and be the technical focal point to integration of system optical phy and CPO electrical subsystems, ensuring its performance.
hands on cross-disciplinary testing efforts and lab work, collaborating with system architecture, optics, silicon, thermal, mechanical, signal/power integrity, and software teams.
characterization and testing of optical links using lab equipment (e.g., oscilloscopes, ber testers, optical spectrum analyzers and simulation tools).
driving product scalability, working with internal partners-qualification teams to transition designs from prototype to high-volume production.
documentation and reporting of design specifications, TEST results, and performance metrics.

we are looking for a chip design micro architect for the networking silicon group.as a chip micro architect at our company networking business unit, you will join a group of passionate engineers to implement the next generation state-of-the-art bluefield dpu SOC and/or connectx nic that deliver breakthrough networking, security, cloud, ai and Storage performance to the ai data centers. as a design micro architect, you will make a real impact in a dynamic, technology-focused ai company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
you will be part of a small and exclusive micro-architecture team and have the opportunity to make a real impact in designing the micro-architecture of the next generation state of the art network card hand in hand with the product architect making sure implementation meets the product goals.
work closely with architecture and design teams to thoroughly understand system requirements and identify micro-architecture solutions, while weighing trade-offs related to performance, area and power consumption
break high-level arch requirements into lower-level design building blocks. focal point for the design team, reviewing implementation and guiding the team.
find bottlenecks early in the development cycle using performance analysis and simulations
use your understanding of the entire chip and system to identify and debug pre and post silicon full-chip issues

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

at our company, we are building the ai factories that power the future of human intelligence! as we scale from thousands to millions of gpus, the "pipes" that connect them have become the most critical bottleneck in modern computing. this is where you come in! we are looking for a visionary senior system architect to lead the charge in defining how we move data at speeds the world has never seen. we want to bridge the gap between silicon and the rack, ensuring our nvlink and infiniband fabrics remain the gold standard for performance. this is a chance to join a team where we don't just follow industry standards-we set them!
you will work at the intersection of signal integrity (si), mechanical engineering, and system protocol design to ensure that our nvlink and infiniband/ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
what youll be doing:
architectural definition: lead the end-to-end definition of high-speed interconnect systems for next-gen ai platforms (e.g., rubin and beyond), focusing on 224g/448g pam4 lanes and beyond.
technology roadmap: evaluate and select pioneering technologies such as co-packaged optics ( CPO ), silicon photonics, and advanced osfp/qsfp-dd form factors.
system co-design: collaborate with asic, thermal, and pcb teams to optimize the "silicon-to-connector" path, minimizing insertion loss and improving signal integrity.
standardization leadership: represent our in industry standards bodies (e.g., ieee 802.3, ocp, msa) to influence the future of high-speed connector and cable specifications.
vendor ecosystem: work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
performance modeling: conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (copper vs. optical).

we are looking for a TEST development engineer to join our team. this role will work as part of a team driven by the development of our company networking and interconnect products. do you have a passion for automation development, TEST program development, code writing and looking for sophisticated and significant topics? we will be happy to have your skills on the team. you will handle various projects across teams, build TEST plans, automate TEST specification and execution. you will continuously innovate and develop scalable, reliable, high-performance systems and tools to enable the next generation of interconnect products.
what youll be doing:
will work on projects across multiple functional teams from different geographies throughout the product lifecycle
develop TEST plans, and execute testing via automation and manually for all supported hardware releases
work with cross-functional teams across engineering, thermal, mechanical, and hw to identify TEST requirements
develop automation and tools for our hardware releases and TEST environment
debug hw & sw failures in interconnect products, isolate the problem, and get to the root cause
design and build technical processes to address business issues
deploy the TEST solution to the production sites and provide support if needed.
train personnel on the required processes and operations of complex TEST systems.
ensure all testing is being conducted in compliance with all safety protocols.

we are looking for a system Engineer to join our failure analysis engineering team under the system product engineering group in the company. as a system failure analysis (fa) engineer, you are responsible for the end-to-end investigation of product failures. you act as the failure analysis product owner diagnosing complex issues that span hardware, software, firmware, and mechanical boundaries of the investigation, synthesizing data from all engineering disciplines to reach a definitive root cause. while you provide the architectural oversight for the team, you remain deeply technical and active in the laboratory environment.
what youll be doing:
hands-on lab investigation: you are active in the lab environment. you perform advanced debugging, characterize system behavior, run reproductions of failures in the lab, and utilize sophisticated lab equipment to validate hypotheses, bridging the gap between high-level data and physical hardware reality.
multidisciplinary failure analysis: lead deep-dive investigations into system -level failures, understand and analyse customer usage for the product, diagnose how software execution, firmware logic, and hardware components interact to cause specific failure modes.
root cause ownership: drive the investigation lifecycle from initial symptom to final physics-of-failure or logic-error identification.
task force leadership: orchestrate and lead cross-organizational technical task forces at the company level. you align experts from hw, sw, mechanical, and npi teams to solve high-priority technical problems.
advanced data & ai integration: define and utilize sophisticated data analysis tools and ai-driven methodologies. you correlate customer failure patterns with production telemetry and rma history to identify hidden trends and systemic risks.
customer quality support: take part in the customer interface by interacting with our customer quality engineers. you provide the deep technical evidence and root-cause clarity needed for quality reports and high-level technical presentations.
strategic lab direction: define the high-level debug strategy and complex TEST plans for the lab. you guide hardware practical engineers on characterization requirements and system -level stress testing.

we are looking for an outstanding architect for a senior system architect role for detailed system arch definition in the network adapters hw team. the role includes fine definition of the product hw architecture, taking into consideration cost/performance/power/thermal/security aspects, working tightly with internal teams (marketing/sw/fw/hw) across the corporate as well as lead customers. focus on latest dpu platforms, both stand alone and integrated in larger systems
what youll be doing:
tailor the hw design architecture together with relevant sw/fw architects (dpu management, power management, security solutions etc.)
become a focal point to other system architects at our company for interface definitions and co-design optimizations
lead hw sku optimization with product teams
define dft features with product engineering team
create new cross-org methodologies for better hw-sw co-designs
take an active role in defining system level features in next gen silicon
take an active role in presenting new solutions to lead customers
take an active role in cost optimization solutions

nvidia's new product introduction (npi) team is growing, and we're looking for a highly motivated and diligent engineering vendor manager to join us. in this critical role, you'll be responsible for the engineering management of our most strategic and technologically advanced suppliers, ensuring the highest quality and reliability of components for our groundbreaking products.
 
nvidia networking division is a leading supplier of innovative end-to-end nvlink, infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance, using nvidias ai solution and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors, including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0.
what you'll be doing:
lead engineering engagement with strategic and critical suppliers for new product introductions (npi) and ongoing production, identify potential risks, critical parameters, and areas for optimization
define and implement clear monitoring and documentation requirements for key process steps to ensure consistency and quality
establish comprehensive quality criteria and outgoing quality control (oqc) procedures at suppliers prior to shipment
monitor and analyze supplier yield data, production metrics, and quality performance to identify trends and drive corrective actions
collaborate closely with internal nvidia engineering teams (design, product, reliability, quality) to ensure supplier capabilities align with product requirements
drive continuous improvement initiatives at suppliers to enhance process control, yield, and overall product quality
conduct supplier technical audits and provide mentorship on standard processes in manufacturing and quality control
act as the primary technical interface between nvidia and strategic suppliers, resolving complex engineering challenges