דרושים » חומרה » senior hardware architect

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology

Define of hardware and system architectures

Research and evaluate algorithms currently used in related applications

Develop complex proof-of-concepts to demonstrate ideas

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

at our company, we are building the ai factories that power the future of human intelligence! as we scale from thousands to millions of gpus, the "pipes" that connect them have become the most critical bottleneck in modern computing. this is where you come in! we are looking for a visionary senior system architect to lead the charge in defining how we move data at speeds the world has never seen. we want to bridge the gap between silicon and the rack, ensuring our nvlink and infiniband fabrics remain the gold standard for performance. this is a chance to join a team where we don't just follow industry standards-we set them!
you will work at the intersection of signal integrity (si), mechanical engineering, and system protocol design to ensure that our nvlink and infiniband/ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.
what youll be doing:
architectural definition: lead the end-to-end definition of high-speed interconnect systems for next-gen ai platforms (e.g., rubin and beyond), focusing on 224g/448g pam4 lanes and beyond.
technology roadmap: evaluate and select pioneering technologies such as co-packaged optics ( CPO ), silicon photonics, and advanced osfp/qsfp-dd form factors.
system co-design: collaborate with asic, thermal, and pcb teams to optimize the "silicon-to-connector" path, minimizing insertion loss and improving signal integrity.
standardization leadership: represent our in industry standards bodies (e.g., ieee 802.3, ocp, msa) to influence the future of high-speed connector and cable specifications.
vendor ecosystem: work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.
performance modeling: conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (copper vs. optical).

we are looking for an outstanding architect for a senior system architect role for detailed system arch definition in the network adapters hw team. the role includes fine definition of the product hw architecture, taking into consideration cost/performance/power/thermal/security aspects, working tightly with internal teams (marketing/sw/fw/hw) across the corporate as well as lead customers. focus on latest dpu platforms, both stand alone and integrated in larger systems
what youll be doing:
tailor the hw design architecture together with relevant sw/fw architects (dpu management, power management, security solutions etc.)
become a focal point to other system architects at our company for interface definitions and co-design optimizations
lead hw sku optimization with product teams
define dft features with product engineering team
create new cross-org methodologies for better hw-sw co-designs
take an active role in defining system level features in next gen silicon
take an active role in presenting new solutions to lead customers
take an active role in cost optimization solutions

as our company, we see problems that others have never encountered. to solve them, we use capabilities and access to technology that few people possess. our group leads, invents, evangelizes, creates architecture, and educates on applying these novel technologies. we are currently seeking a hard-working senior system and hardware timesync architect who flourishes with these types of challenges to join our time synchronization architecture team.
in this role, you will be exposed to the newest technologies and will help define how our gpus, cpus, and networking devices use timing to power extraordinary products and applications. specifically, you will focus on next-generation innovative, scalable, and power-efficient timesync solutions. by working across hardware and software stacks, you will support sophisticated ai acceleration and drive industry-wide standardization. if you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.
what youll be doing:
master our time synchronization technology
define of hardware and system architectures
research and evaluate algorithms currently used in related applications
develop complex proof-of-concepts to demonstrate ideas
collaborate with software architects to define new features and robust sw-hw interfaces for diverse networking use cases.
drive standardization and interoperability to support broad industry adoption.

we are seeking a highly motivated  system  architect to join our team of experts and help shape the future of ai & cloud computing. our next-generation bluefield dpus and connectx nics will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in ai research to cloud & Storage servers.
what you'll be doing:
define server platform architecture for next generation data center products for ai and cloud, focusing on dense networking solution.
design is highly restricted in space, power and thermals.
define board level and system management architectures for the different platforms
define board level integration and system model for reset, recovery and boot
partner with product, software, design and platform engineering groups for converging plans according to requirements
work with the software team on software and hardware apis
research next generation needs