דרושים » חומרה » senior asic architect

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. we make outstanding artificial intelligence happen and accelerate open-ais chat-gpt, for example. we believe in our people and products and seek excellent people to join us!
we're looking for a hardware u/architect for our switch division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both ethernet and infiniband. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system requirement and help define the por of our switch product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand ethernet, infiniband and nvlink protocols.

our company networking is a world-leader in building the most powerful supercomputers in the world which drive the ai and hpc industry. these rely on high performant network asics which connect gpus at scale for efficient data transfer and compute.
we are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. the role is cross-disciplinary, collaborating with hardware and software teams across the wider company.
you will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.
what you'll be doing:
develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for our next generation of switches.
learn and understand the switch asic across all performance related aspects
focus on switch hardware modeling.
analyze and model the communication patterns of key DL, gai inference and training applications.
explore innovative ideas to improve and optimize our chip systems performance.

our company networking is a leading supplier of end-to-end ethernet and nvlink intelligent interconnect solutions and services for servers, Storage, and hyper-converged infrastructure. the company hw microarchitecture group is looking for an extraordinary solution architect to participate in helping our customers to get the maximum performance from our network products. the successful candidate will show strong background in chip design (arch, microarch, design, dv), excellent system view, ability to work independently, good communication and motivation to solve sophisticated problems.
 
what youll be doing:
help customers get the best performance from our products.
debug sophisticated customers issues.
come up with solutions for current and future products.
work with teams and customers from around the world.
partner closely with our field engineers and architecture.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip design group (socd) is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams.
what you'll be doing: implement chip level design through collaboration with cross-functional teams (functional design, dft, design verification, system verification, sta, and physical design).
be exposed and work on a variety of functional and structural challenges. including functional debug, physical design readiness, emulation, resolve design quality issues.
daily work involves aspects of chip level design, including partitioning, cdc, rdc, trial synthesis, design quality checks
taking part in flows development and deployment.

we are looking for best-in-class chip design engineers to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
join tel-aviv/beer-sheva group, working on verification in the field of encryption accelerators.
verification of chip blocks/entities according to specifications under challenging constraints and with high orientation to power, area and performance.
daily work will involve verification and might involve any or all aspects of chip development including micro-architecture.
work closely with firmware and other groups around the globe.
work mode: hybrid home-office.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
lead the end-to-end execution, tracking, and convergence of chip-level cdc and rdc for complex socs across all ips and partitions.
plan and orchestrate cdc/rdc signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
run and maintain cdc/rdc flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
triage violations efficiently: root-cause to rtl, constraints, tool setup, or ip models; prioritize and drive fixes to closure with owners.
verify reset architecture and rdc robustness (reset domain intent, release sequencing, glitch detection, fanout).
author and review cdc/rdc constraints, waivers, and justifications; ensure auditability and signoff quality.
automate runs, report parsing, dashboards, and kpis for closure tracking using scripting and data tooling.
partner with rtl, dv, dft, sta, pd, and architecture to align fixes, manage ecos, and protect cdc/rdc quality during late design changes.
define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
continually improve methodology and training to prevent recurring cdc/rdc issues and accelerate convergence.

we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!