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we are now looking for an engineering lab technician in the optical assembly team to support developing new nvidia's products. this newest member will collaborate with an innovative multidisciplinary world-class team of engineers to help build and develop our industry leading transceivers. in this role you will run multiple sophisticated assembly platforms, so there will be plenty of opportunity for learning new skills related to the field of advanced packaging. the primary responsibility is to support our engineering teams during development to ensure outstanding quality gpu server products may be released to the market and delight our customers so that ai scientists and datacenter operators can achieve their professional aspirations using nvidia technology. the new lab team member will work independently to complete daily tasks according to priorities, demonstrate a passion towards system level product quality, and should be comfortable in the lab environment.
what youll be doing:
participating in development of new packaging technologies while working tightly with process development team.
prepare and conduct experiments to TEST new assembly technologies and materials.
operation and maintenance of variety of platforms involved in process of packaging - wire bonding/pick&place/active alignment.
maintain laboratory hardware and handle materials.

we are seeking a skilled failure analysis (fa) engineer with expertise in x-ray inspection techniques to join our av platform team. the ideal candidate will specialize in using advanced x-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability what will your job look like?
perform detailed failure analysis using x-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
interpret and analyze x-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
develop and optimize x-ray inspection procedures and protocols for failure analysis and quality control.
prepare TEST specimens: cutting, mounting, grinding, polishing and chemical etching
collaborate with product engineering, Quality Assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
support reliability testing and failure mode analysis for new and existing products.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our mission is to organize the world's information and make it universally accessible and useful. our team combines the best of ai, software, and hardware to create radically helpful experiences. we research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. we aim to make people's lives better through technology.as a power and signal integrity engineer, you will be responsible for the design and characterization of signal and power integrity of our ic designs. you will design the external electrical interfaces of the device, from their signal/power-integrity and electrical usage perspectives.you'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our ic designs meet systems design budgets and achieve the highest performance. you will work with systems architects, asic design, systems engineers, and partner cross-functionally with teams and external vendors/partners.the ml, systems, & cloud ai (msca) organization at designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
design and optimize power distribution networks (pdn) across chip, package, and board levels. this includes managing power/ground planes, decoupling capacitors, and power gating strategies.
conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (ssn/sso), voltage drops (ir drop), and electromagnetic interference (emi).
implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like upf/cpf.
generate precise electrical models (e.g., s-parameters, spice models) for components such as packages, pcbs, and connectors for use in simulations.
execute lab measurements utilizing TEST equipment like oscilloscopes, vector network analyzers (vna), time domain reflectometers (tdr), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

Our New Product Introduction (NPI) team is growing, and We are now looking for a Chip Engineering Operations Program Manager! The Engineering Operations group has an immediate opening for a top Program Manager. This group is responsible for the silicon schedule from bring-up to production release. We are looking for individuals who thrive in a dynamic environment, and are not afraid to roll-up his their sleeves and get their hands dirty. We desire a self-starter, with great communication skills; as well as a leader, with a deep sense of commitment. You will be responsible for developing wafer forecasts, schedule generation and management, supporting cross-functional teams, and mitigating any programmatic risks. You will also review and improve processes, and handle prototype demand.

What you'll be doing:

You own silicon bring-up schedule from power on to production release.

Negotiate silicon and board demand with teams and drive a bottom-up forecast.

Oversee and manage chip and board allocations across the company.

Lead prototype chip delivery to internal customers.

Track and coordinate engineering deliverables, key milestones and qualification/validation tasks in the new product introduction phase.

Identify and mitigate risks to schedules and programs.

Communicate status to cross-functional teams as well as upper management.

Continuously evaluate internal tools and processes and drive fixes to improve productivity.

Create new and fix existing processes between different teams.

Drive implementation of SW tools for data analytics and process evaluation.