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We are looking for a System Engineer who "speaks" both Network and Code. In this role, you will be the architect of the systems connectivity, designing how our devices communicate over wired LAN infrastructures and ensuring the software architecture supports robust, high-throughput data flow. You will bridge the gap between IT network configuration and R&D software development.

Responsibilities:
System Network Design: Define the networking architecture for complex systems, focusing on Wired LAN configurations, switch management, and topology planning.
E2E device to platform SW features: Collaborate with SW teams to define system-level software features - for example security, configurations, etc...
Network Integration: Lead the integration of system components into customer IT environments (Subnets, VLANs, Firewalls).
Hands-on Coding: Write production-grade code or advanced scripts for system automation, network simulation, and performance testing.
Bottleneck Analysis: Analyze data flows to identify network congestion or software inefficiencies and propose architectural changes.
Security: Define and implement network security protocols (PKI, penetration resilience) within the system design.

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer at nvidia's networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

we are looking for a power u-arch senior engineer. our company is known as a world leader in providing energy-efficient high-performance products and we continue to invest in the research and development of hyper-efficient SOC architectures. we are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors and verticals. come join our applied power team to develop state of the art dpu products.
what you'll be doing:
lead a micro-architecture of power features such as: power management, logical power features, etc
work with dpu arch team on power features definition.
understand the workload characteristics for dpu workloads at system scale to drive new hw/sw features.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
what you will be doing:
work in a combined design and verification team which develops core units within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, full-chip, fw and post-silicon validation.
your daily work will involve all aspects of design verification: planning, coding, coverage and integration

Were hiring an experienced verification engineer to join our team developing advanced telecommunications ASIC/FPGA products. You will join RADs family, as part of our team in Beer-Sheva.



Responsibilities:
Build and maintain verification environments (SystemVerilog/UVM or Specman)
Develop test plans and run constrained-random & directed tests
Debug, analyze coverage, and work closely with design teams
Contribute to methodology and process improvements

we are now looking for an arch simulation manager to join our nvidia networking team! as a switch-arch simulation manager in nvidias networking business unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of nvidias cutting-edge switch products. this is a unique opportunity to make a real impact at the heart of nvidias ai and hpc revolution, while working in a fast-paced, innovative environment. you will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of nvidia networking products. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of hardware Verification engineers focused on arch performance validation of complex digital designs.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.

we are now looking for a senior verification manager for our fc switch silicon team. as a fullchip verification manager in networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a fc team, responsible to integrate and verify the switch at system level
lead and grow a team of fullchip Verification engineers
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries
provide technical guidance, mentoring, and support to engineers in the team.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw
dynamic verification environments planning for units infrastructures and system level
work with design/verification team which develops core units within the switch silicon.

we are looking for a senior firmware Verification engineer to define, develop and maintain verification for our ethernet switches. this role offers you an excellent opportunity to participate in the development process of switches and gain a deep understanding in hardware, firmware and software systems in a rapidly growing field.
what youll be doing:
closely work with sdk/fw r&d architecture and QA to define, write and implement TEST plan for out product existing new features.
be responsible for verification and delivering different networking features.
define, develop and maintain verification procedure and reference model infrastructure - make TEST suites robust.
work with continuous integration system, regression tools, automate builds, run TEST suites and analyzing results
we are an equal opportunity employer and value diversity at our company. we do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

we are looking for a dedicated SOC clocks design automation engineer to join our networking silicon team. in this role, youll focus on developing and supporting clock-related design flows and methodologies for SOC and networking chips, ensuring efficient and high-quality design implementation. youll also chip in to SOC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. introduction
what you'll be doing:
develop and maintain design automation and methodologies for SOC and networking clock flows.
collaborate with design, sta, and project teams to ensure timely and high-quality design closure.
develop and improve SOC top-level automation scripts and flows built upon existing infrastructure and tools.
support SOC integration and construction flow activities across multiple projects.
assist in timing, power, and noise analysis to ensure efficient performance.

we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.

we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

ethernet switch firmware team is looking for a hardworking firmware manager to take part in leading and developing the firmware / hw interface in the next generation state of the art switch products.
as a member of our fw ethernet team, you will be responsible on a team of firmware engineers. it is expected that you will manage and guide the team for critical items.
this role offers you an excellent opportunity to accomplish something new, enabling understanding of hw and sw in a rapidly growing field while solving interesting technical issues and providing feedback to the hw team to improve the next asic generation.
what you will be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the core of switch networking firmware.
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
work in pre and post-silicon development environments of next-generation switch networking products.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the hw/fw/sw relationship.
innovate! bring networking products to shine in customers view

we are seeking a dedicated firmware engineer to join our nic firmware core team in beer-sheva/tel-aviv. you will contribute to the development of brand-new networking adapter technologies, elevating the performance of current and future our company devices. our company develops innovative and next-generation networking devices that are known for their outstanding performance and power efficiency. the position involves all aspects of firmware development, including design, micro-architecture, software interfaces, and verification. we are seeking a dedicated and motivated engineer who will contribute to the development of advanced technology network adapters. you will also have the opportunity to create features for leading cloud computing providers and high-performance computing networks.
what youll be doing:
take a part in the design, development, TEST, debug, and optimization of low-level firmware layer on next-generation network adapters up to package release
analyze, integrate, support, and debug low-level firmware layer on verification environments
collaborate with firmware, software, and architecture teams to analyze, design, and debug legacy and new low-level firmware flow
improve our team processes including design and implementation of new methodologies, automated processes.