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We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

We are looking for a best-in-class Senior Full-Chip Verification Engineer with a strong infrastructure mindset to join our Networking Silicon team. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level, while also driving the evolution of the simulation infrastructure powering our verification flows. You will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the world's most advanced data centers, in a meaningful, growing environment where you make a huge impact in a technology-focused company.

What you'll be doing:

Simulation Infrastructure & Acceleration: Identify bottlenecks in the verification flow and engineer creative solutions - building frameworks, optimizing regressions, and accelerating simulation throughput through innovative tooling.

Multi-Language Development: Work across a diverse technology stack (SystemVerilog/UVM, Specman, Python, C/C++, scripting) - writing code and solving problems at every layer, from RTL testbenches to infrastructure utilities and automation.

System-Level Debug & Analysis: Gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance.

AI-Enhanced Development: Accelerate development by leveraging cutting-edge AI coding tools and frameworks - applied to both verification and infrastructure challenges.

Cross-Team Collaboration: Work closely with multiple teams within organizations such as Architecture, u-arch, Firmware and all units inside the NIC.

We are seeking a Front-End Integration Engineer for the NIC Silicon group. Join our team in our Networking business unit and be part of the innovative build and implementation of the next generation Network Adapter Silicon chips. Contribute to the development of powerful communication devices.

What You'll Be Doing:

Own and maintain Continuous Integration pipelines. Monitor, complete, and fix daily and nightly CI flows in front-end build areas. These include Lint, Synthesis, Equivalence Checking and Simulation.

Automate EDA Flows: Build, develop, and maintain robust automation scripts using Python, Tcl scripting, and Shell to integrate EDA tools (Synopsys, Cadence) into automated build pipelines.

Manage Perforce Integration: Maintain multi-IP branch/stream strategies, manage workspace specs, complete hardware build drops, and handle release labels/tags in Perforce (Helix Core).

Support Engineering Teams: Act as the primary point of contact for RTL and verification engineers to debug flow crashes, bottlenecks, environment setups, and CI failure reports.

Enforce Quality Gates: Implement automated check-in and change list triggers to run sanity checks, linting, and style enforcement before code is committed to main streams.

Optimize Infrastructure: Monitor compute farm resources (LSF) and storage usage to reduce pipeline runtime and improve overall execution efficiency.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are now looking for a Power Optimization and Analysis Engineer! We prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our Switches product line.

As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.

What You'll Be Doing:

Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.

Develop and share best practices for performing pre-silicon power analysis.

Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.

Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.

Select and run a wide variety of workloads for power analysis.

Prototype new architectural features in Verilog and power analysis.

Our Networking System Product Engineering group is looking for an excellent Software Engineer. The position requires an understanding of HW and SW to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers. You will lead the development of our products and raise the bar of the software development quality in the group. We have crafted a team of extraordinary people, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

What youll be doing: 

Design and develop automated tests for networking Switches and Adapters while working closely with the HW, ASIC, and SW Engineering teams to achieve a reliable test with high coverage.

Exposed to various aspects of design, DFT, and test of our next-generation network products.

Take a significant part in the definition and development of tests from the development level to the final test of Network-Systems.

Utilize test suites to find, debug and resolve problems with production process.

Ability to drive projects to full execution in time and working under pressure of schedule and multi project environment.

Supporting and fixing bugs of existing code. Supporting production lines for: deployments, patches, maintenance.

Test Verification and Validation (both HW and SW). Troubleshooting and streamlining/optimizing our testing procedures.

We are seeking an experienced Senior Firmware Engineer to join our NIC Firmware Core team, with a special emphasis on simulation for network adaptors and verification infrastructure. Youll be part of a forward-thinking team dedicated to advancing the tools and frameworks that are used to develop the cutting-edge networking adapter technologies. Your role will be to drive the success of our current and upcoming networking devices by working across various platforms, including C++ object-oriented simulation, verification frameworks and C layer interfacing hardware and firmware.

What Youll Be Doing:

Take part in implementing and assimilating frameworks for Design and Verification both for real-time and simulator environments.

Addressing and solving automation and performance challenges.

Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows.

We are looking for an experienced Firmware Engineer to join the NIC Firmware team at the Yokneam site. The Firmware team develops cutting edge networking features for cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With talented engineers around the globe, the work environment is dynamic, meaningful, and fast-paced.

What you will be doing:

Work closely with the architecture and different software design teams.

Implement new features in the core of our NIC firmware in pre and post silicon environment.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Gain a deep understanding of system debug, networking technology and stacks, as well as the HW/FW/SW relationship.

You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed.

We are seeking an experienced Senior Software Engineer to join our NIC Firmware Core team, with a special emphasis on simulation for network adaptors and verification infrastructure. Youll be part of a forward-thinking team dedicated to advancing the tools and frameworks that are used to develop the cutting-edge networking adapter technologies. Your role will be to drive the success of NVIDIA's current and upcoming networking devices by working across various platforms, including C++ object-oriented simulation, verification frameworks and C layer interfacing hardware and firmware.

What Youll Be Doing:

Develop a network adapter simulator that will be used for both development and testing of pre-silicon networking features.

Take part in implementing and assimilating frameworks for Design and Verification both for real-time and simulator environments.

Addressing and solving automation and performance challenges.

Collaborate with chip design, software, and architecture teams to define and craft legacy and new firmware flows.

We are looking for a Storage Software Architect to join the architecture group. You will be part of a team that shapes the next generation of storage for AI: training, inferencing, KV cache, RAG and more. Utilizing the best from our network products, DPUs and NICs, working closely with hardware architects, SW architects and external customers, defines the programming interfaces, protocols and management. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow. We work, think and learn as a team. We thrive in a deeply strong environment and we're passionate about a culture that demands innovation and the highest standards. The rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.

What youll be doing:

Define how storage for AI clusters should look like.

Research and analyze AI storage workloads, POC ways to optimize them.

Design the storage SW stack for AI, APIs, and offloads.

Lead hands-on POCs.

Drive HW features to next generation of DPUs and NICs.

Rapid Medical is a fast-growing medical device company focused on developing, manufacturing, and selling innovative devices for endovascular interventional procedures. We are looking for a talented and creative engineer to join our R&D team and be a key player in our future development. LOCATION: Yokneam, Israel
SCOPE & RESPONSIBILITIES:
* Design and develop innovative neurointerventional medical devices as part of the R&D team.
* Plan and execute verification tests for new prototypes and new products
* Prepare product documentation, including DHF and DMR
* Analyze test results and author detailed engineering reports
* Collaborate with Quality and Regulatory Affairs to ensure design control compliance
* Lead design transfer activities, support pilot production, and transition products into manufacturing

We are now looking for a motivated Chip Architect to use your creativity to work on the ConnectX network adapter with the highly inventive and knowledgeable team.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Work on proof of concepts and advance development projects.

Perform research and analysis for current and future architectures.

Craft product design specifications.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

The company's Advanced Research (ARG) team in Yokneam is looking for a Senior Electro-Optical / Board Design Engineer for research and development. The ARG group is doing research and development of next-generation electro-optical devices and EO sub-systems for high-speed communication. Our solutions include laser diodes, photo-diodes, modulators, and electronics for use in optoelectronics. The selected candidate would work as part of a multi-disciplinary team, composed of engineers and researchers, supporting the development of future components and systems, for current and next generations.


What youll be doing:

Take part in research and development of next-generation electro-optical devices and EO sub-systems for high-speed communication.

The candidates tasks will include electrical specification of EO sub-systems and evaluation boards, schematic design, component selection and characterization, layout considerations and implementation, Fabrication and Assembly guidance.

Hands-on development and testing within Data Center interconnect lab environment.

We are looking for a performance modeling architect to join the team and shape, optimize, and explore our future networking chips and solutions. The role is cross-disciplinary, collaborating with hardware, software, and research our teams across the wider. You will lead workgroups towards technical solutions that will influence the heart of cutting-edge networking products. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation of networking solutions.



What you'll be doing:

Thoroughly understand our networking solutions across all performance related aspects.

Develop a C++ simulation model to define and evaluate architectural options for our next generation of networking products.

Understand different trade-offs related to solving performance bottlenecks.

Collaborate and lead technical solutions within architecture, research, hardware, and software teams.

Analyze and model the communication patterns of key DL, GAI, inference, and training applications.

Explore innovative ideas to improve and optimize our chip systems performance.

We are seeking a Senior System Management Architect to join our growing team. You will be the resident expert for system management, ensuring that AI factory management components (BMCs, MCUs, CPUs, network switches and CPLDs) operate in perfect unison. You will own the lifecycle management specifications for AI factory platforms - from factory provisioning to day-one deployment. If you enjoy studying a high-level system diagram and then immediately diving into the system-level buses and interface signals topology and the associated host management protocols modeling required to make it work, this role is for you.



What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery, and reset flows for AI factory sub-systems.
Ensure system-level architectural alignment and orchestrate seamless coordination between all the AI-Factory building blocks: GPU, DPU, CPU, Switch ASIC, NIC ASIC, BMC, and peripheral components.

Protocol Implementation & Guidance: Specify the use of standard management protocols (Red-Fish, NSM, PLDM, SPDM, MCTP, NC-SI) across sub-system interfaces to implement the management tasks.

Hardware/Software Intersect: Define system-level hardware and software behavior, including CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets).

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate with Production, Hardware and Firmware Engineering, ASIC FW/Driver teams, SW/NOS teams and QA to translate architectural specifications into implementable, testable solutions.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide development and factory production.