לוח משרות דרושים מהנדס מחשבים, לחיפוש זה נמצאו 194 משרות

Required Chip Test Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Nuvoton Israel is a leading supplier of custom SoC and security hardware solutions for the computing and server markets. We are looking for a motivated Software Engineer to join the CAD team at Nuvoton and grow with us over the long term. As a CAD Developer, you will participate in Physical Layout Verification (DRC/LVS/ERC) of semiconductor chips and develop and maintain in-house CAD infrastructure and automation tools used by engineering teams.

As a SI/PI Engineer on the Nitro team, you'll apply your Signal Integrity and Power Integrity expertise to next-generation cloud infrastructure hardware. You'll perform SI/PI analysis, simulation and validation on cutting-edge high-speed digital systems, contributing to products that directly impact our customers.

Key job responsibilities
- Simulate, correlate, and validate SI/PI aspects of PCB and system-level designs.
- Collaborate with Package design, SerDes and DRAM IP providers, firmware, and manufacturing teams.
- Analyze and optimize power delivery networks from card to system level.
- Support hardware bring-up, debug, and validation with hands-on lab work.
- Review and provide technical feedback with internal and external design teams.
- Contribute to design guidelines and best practices based on measurements and analysis.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers us at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.
It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack.
It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.
It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development.

As a Senior Design Verification Technical Lead on the Graviton team, you will be responsible for
leading the verification of complex SoC sub-systems, driving cutting-edge verification
methodologies, and ensuring our next-generation Graviton server SoC meets the highest quality
bar before reaching silicon.

What You'll Do:
- Develop and execute verification plans for IO sub-systems- covering interconnect.
protocols, peripheral interfaces, and system-level integration
- Verify IO sub-system features including interconnect protocols, various accelerators engines.
- C embedded SW programing and SW debug skills
- Build and maintain UVM-based verification environments for IO sub-systems.
- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
- Contribute to performance verification - ensuring micro-architectural
implementations meet performance targets alongside correctness.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

Come join the AWS Agentic AI science team in building the next generation models for intelligent automation.

We are looking for world class researchers with experience in one or more of the following areas - autonomous agents, API orchestration, Planning, large multimodal models (especially vision-language models), reinforcement learning (RL) and sequential decision making.

As a Signal & Power Integrity Engineer on the Nitro team, you'll work on next-generation cloud infrastructure hardware while developing your skills in Signal Integrity and Power Integrity. This is an opportunity to learn SI/PI analysis and simulation while applying your hardware design knowledge to solve complex challenges in high-speed digital systems. You'll be mentored by experienced engineers and contribute to products that directly impact our customers.

Key job responsibilities
- Design and debug high-speed digital circuits for K2 cards and server platforms.
- Learn and apply SI/PI simulation methodologies for PCB and system-level designs.
- Collaborate with Package design, SerDes and DRAM IP provider, firmware, EC2, and manufacturing teams.
- Perform signal integrity analysis for high-speed interfaces and SerDes channels at the advanced of the technology.
- Analyze and optimize power delivery networks from card to system level.
- Support hardware bring-up, debug, and validation with hands-on lab work.
- Participate in design reviews and provide technical feedback with internal and external design teams.
- Work with cross-functional teams to resolve signal quality and power integrity issues.
- Contribute to design guidelines and best practices based on measurements and analysis.

We are looking for talented engineers to help us develop a semiconductor platform based on revolutionary architecture.
Take part in the development of cutting-edge products within a disruptive system architecture. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. Our Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented physical design implementation engineers to join our excellent Physical Design team, which develops our next generation of products for the cloud market.

Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macros and clusters level, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsis and Cadence.
* Engaged in defining implementation and signoff methodologies.

We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.

We are seeking for Platform Integration Engineer to own the development, testing, and monitoring of the manufacturing health of our Graviton products integrated into MLA Trainium product. You will be part of a team integrating new silicon, hardware, firmware, and software into a revolutionary system architecture.

Key job responsibilities
- Lead product integration from definition phase through mass production, including: Hardware-Firmware integration and validation, development and implementation of manufacturing test flows, system validation and qualification and production readiness verification.
- Define and implement screening test content for both production line and data-center environments.
- Drive continuous improvement of operational health monitoring and debugging capabilities.
- Collaborate with cross-functional teams to resolve integration and production issues.
- Implement test flows for improving product operational health at manufacturing sites.
- Integrate knowledge and data from customers and data sources for fast resolution of operational issues.
- Maintain quality documentation and collateral in order to improve manufacturing operations.
- Travel to manufacturing sites as needed (approximately 3-4 times per year, 1 week duration per trip) to support integration, validation, and operational improvements.

We're looking for a talented Chip Design Engineer to join our Nitro team in Tel Aviv and help shape what comes next.

What you'll do:
*Take an active, hands-on role in developing the next generation of the Nitro platform.
*Own critical IP blocks end-to-end - from architecture through tape-out.
*Collaborate with a world-class, fast-moving design team and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
As a Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor AWS cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.