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Our networking insights architecture group is looking for a motivated switch performance modeling architect to develop a cycle accurate network simulator with the purpose of analyzing and improving switch performance, used in AI and High-Performance Computing workloads. You will solve complex problems and develop innovative software and hardware solutions using a simulation tool, and be instrumental in determining the architecture of our next generation networking solutions.
What you'll be doing:
Develop cycle-level simulation components to evaluate and analyze micro-architecture and architectural solutions.
Focus on nvlink and spectrum switch hardware modeling, for better performance and optimizations
Analyze and model the communication patterns of key applications.
Explore innovative ideas to improve our systems performance.

we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Join our team as a Senior Power and Performance Architect - Networking, influencing the future of network systems at our company.
What you'll be doing:
Develop, model, and validate groundbreaking power and performance optimization techniques for network fabrics, components (NICs, Switches), and systems. Collaborate closely with cross-functional teams including silicon design, system architects, software/firmware engineers, performance analysts, thermal engineers, and AI researchers to ensure end-to-end power and performance optimization. You will determine strategies that successfully implement flawless performance and power efficiency in our ambitious projects!

we are looking for best-in-class Senior VLSI integration Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Implement Chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design) .
Be exposed and work on a variety of functional and structural challenges. Including functional debug, getting ready for physical design, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks
Taking part in flows development and deployment.

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
At our company Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet Layout owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
What you'll be doing:
Be part of a cross-business-unit team and own the high-speed IP integration.
Build a Chiplet floorplan layout design from early assembly/planning through implementation and signoff.
Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
Define and implement efficient, high-quality Full Chip/Chiplet physical design tools, flows, and methodologies.
Gain hands-on experience implementing the partition-level BE design (RTL2GDS).

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Developing and deploying automation flows which support SOC level design
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We are looking for a CDC Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
You will play a major role analyzing the design and driving fixes as well as developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) constraints and methodology for our SOCs across block level, cluster level, and/or full chip level.
Responsibility for analyzing and optimizing the CDC and RDC sign-offs.
Develop and maintain key CDC/RDC checks and associated sign-offs for SOCs.
Help in driving frontend and backend assertions needed to support CDC/RDC constraints and assumptions.
Learn and understand the switch u/architecture to support the design and verification teams.

we are on the lookout for a dedicated and driven Software Engineer to join our dynamic VLSI Design Automation team. This team focuses on the development of VLSI CAD tools and web applications, and is responsible for managing and maintaining high-quality VLSI infrastructure, including compute and storage for the Backend Networking team. We seek a passionate engineer eager to effectively manage compute and storage, develop scripts, automate processes, and create dashboards and applications. Our ideal candidate is someone with experience in VLSI methodologies, data-driven, eager to learn, and possesses strong interpersonal skills.
What youll be doing:
Oversee and optimize compute and storage resources, ensuring operational efficiency and success of VLSI projects. Develop and maintain scripts and automation tools to streamline infrastructure tasks.
Engaging in the entire lifecycle of tool and web application development, which includes backend, frontend, data storage design, UI/UX design, testing, deployment, and maintenance.
Design, implement, and maintain dashboards for monitoring and reporting on infrastructure performance and usage.
Challenge existing VLSI methodologies to have better tools and flows.

We are seeking a highly motivated Chip Architect to join our team and help shape the future of next-generation high-performance networking. our companys next-generation Ethernet and NVL switches are at the core of the worlds most advanced compute clusters from powering AI factories to scaling NVL-based GPU systems used in training/inferencing of the largest foundation models. As a Chip Architect at our company, you will play a central role in defining the architecture of these high-bandwidth, low-latency switches. Your work will directly impact how AI supercomputers, hyperscale data centers, and cutting-edge research platforms communicate at scale. You will join a team with a strong track record of first-in-the-world products and help deliver the next leap in networking technology.
What You'll Be Doing:
Define the end-to-end architecture and full feature set of next-generation NVL and Ethernet switch chips across all stages of the product lifecycle from early concept to deployment.
Develop architectural specifications and design guidelines, and drive trade-off analyses across multiple architecture options.
Lead research and exploration of future architectures, including innovation that contributes to patent development.
Collaborate closely with cross-functional teams including other architecture groups, logic design, firmware, system software, and research to ensure successful execution and integration.
Act as a technical leader and subject matter expert, mentoring others and driving architectural excellence across the organization.