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We are looking for an experienced System Validation Engineer to join our Runtime Validation Team.
In this role, you will be responsible for validating runtime stack components for classic and generative AI applications, ensuring their reliability, performance, and robustness. Your work will have a direct impact on our products, shaping the quality and stability of AI-driven solutions used in real-world applications.
Responsibilities
Design, develop, and execute validation test plans for runtime stack components, neural core firmware, and drivers, while accompanying them throughout the entire feature life cycle, from
design and integration through automation and release, ensuring ongoing support and adaptation of tests as the product evolves.
Develop automation frameworks and testing tools in Python and C++.
Analyze test results, debug issues, and work closely with software and hardware teams to drive resolution.
Ensure continuous integration (CI) pipelines maintain high test coverage and efficiency.
Optimize validation strategies for classic and generative AI workloads.

Required Data Flow Compiler Engineer
Description
A leading high-tech company, developing top-performing AI processors for edge devices in various industries. We combine an extensive understanding of the way neural networks operate, with our teams expertise in SW and HW architecture, to develop products that transform the way we use machines to perceive and analyze the world around us.
Our company is led by a group of experts from a wide range of disciplines, combining experience from elite intelligence units as well as leading tech companies in Israel and abroad, with a track record of executing complex projects from the ground up. As an AI chip company, we believe that AI can help us create a better, safer, more productive, and more convenient world. For this to happen, AI needs to be available at scale and on the edge.
To this end, our team of hardware and software leaders is developing top-performing AI processors, dedicated to AI tasks on edge devices in a wide variety of applications and industries including smart cities, automotive, manufacturing, agriculture, retail, and many more. With hundreds of customer programs around the world, and a wide ecosystem of software and hardware partners, we are leading the edge AI revolution.
In this position
As a team member of the team, you will work on several challenging fronts, implementing different algorithms for resource allocation, mapping, HW-specific features, and optimizations in C++. Help build and develop our dataflow compiler, an innovative unique toolchain that takes real-world AI models and compiles them to our breakthrough processors.
The role involves a deep understanding of our architecture and has an extensive direct impact on our products.
Responsibilities
Design and develop a multidisciplinary system for machine learning.
Work in different SW environments: C++, Python, AI frameworks.

We are looking for a highly experienced Logic Design Engineer who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding experienced DevOps Engineer customer base.

Join us in this exciting journey to redefine the future of quantum computing.

Responsibilities:

Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)

We are looking for a Senior Test Automation Engineer to join our Product Engineering Team. In this role, you will be responsible for designing and implementing automated test programs for hardware validation and production testing. You will work closely with hardware engineers to define test strategies, ensure seamless SW-HW integration, and optimize test environments to improve efficiency and reliability.

Key Responsibilities

Define and drive team SW methodologies to develop scalable and maintainable test solutions by using SW best practices
Develop and maintain automated test programs for hardware validation and production testing.
Analyze hardware schematics and component datasheets to understand DUT (Device Under Test) behavior.
Collaborate with hardware engineers to define, implement, and stabilize automated test environments.
Enable HW operation through software-driven testing methodologies.
Debug SW-HW integration issues and optimize test sequences for robustness and efficiency.
Maintain test documentation, analyze test results, and contribute to yield improvement efforts.

We are seeking a highly skilled Hands-On Engineer to join our Quantum Integration Team, ensuring seamless integration of multi-layered systems. This role requires close collaboration with cross-functional teams to debug, validate, and integrate complex interfaces while ensuring end-to-end functionality.

Join us in this exciting journey to redefine the future of quantum computing.



Key Responsibilities:

Integration of multi-disciplinary systems, ensuring smooth operation across different layers.
Debug and troubleshoot issues arising in the integration process.
develop integration and validation tools.
Collaborate with architecture, logic design, verification, compiler, and embedded teams

We are looking for a Verification Engineer who embodies ambition and positivity, who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfil the evolving needs of our expanding customer base.

The Verification engineer we look for will be a highly talented and motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists.

Responsibilities:

Practicing the full range of verification aspects
Creating a verification environment from scratch (drivers, monitors, coverage...)
VIP (DDR/PCIe/AXI) integration
Defining verification sequences via a complex control-flow constraint set
System understanding of a full-stack product with strong HW-SW coupling
Reference model integration
Test plan definition
Defining verification flows and creating the proper infrastructure to support it

We are looking for a super talented engineer to join our team and build architectural model of a quantum control system.

We are looking for a motivated person, who is a real team player and can collaborate closely with engineers from other disciplines and quantum physicists

Responsibilities:

Working in all fronts high-level architectural solutions to low-level design constraints
Working across multiple teams and methodologies
Designing a complex IP to be used both internally by various R&D teams and externally for our customers as a stand-alone product
Designing a flexible and integration-able model to allow referencing from various programming languages (UVM, Java, Python, Kotlin and C++) as well as coupling it to a behavioral quantum simulator

As a Tech Leader in the AI Algorithm Engineering group, you will play a pivotal role in both managing end-to-end AI research and development efforts and hands-on involvement in key-initiatives. Your responsibility will include design, implementation, guidance and mentoring for team members, and representing the AI considerations in cross-team discussions. You will leverage your extensive experience to lead multiple AI projects, and will be a key figure in leading successful execution and in finding creative solutions to difficult bottlenecks, across data, AI, engineering and product considerations.
Responsibilities:
Lead the design, development, and implementation of accurate and robust AI algorithms for medical data with a hands-on approach.
Collaborate with cross-functional teams, including data scientists, software engineers, product managers and clinical data experts, to ensure AI considerations have a profound impact on R&D and Product decisions across the projects.
Design and conduct research and experimentation to improve algorithm performance and accuracy.
Stay at the forefront of the latest advancements in AI and machine learning, particularly in the medical domain, and drive their adoption within the team.
Oversee multiple projects, ensuring successful execution, timely delivery and alignment with product and business objectives.
Provide strategic direction and technical mentoring to elevate the capabilities of the AI team.

Be part of a team to verify complex digital design blocks at subsystem level or full chip level by fully understanding the design specification and interacting with design engineers to identify key verification scenarios.
Create and enhance constrained-random verification environments using UVM SystemVerilog or create complex multi core based C tests using reusable C test libs.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

Define architecture and micro-architecture features, write specifications, and understand implementation tradeoffs (e.g., performance, power, frequency, etc.).
Define the CPU block level design document (e.g., interface protocol, block diagrams, transaction level flow, control registers, pipelines, etc.).
Perform RTL development process (e.g., coding and debug in Verilog, SystemVerilog, or VHDL), function/performance simulation debug, and Lint/CDC/FeV/PowerIntent checks.
Contribute to the SoC level integration, and participate in synthesis, timing/power closure, and silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC-level verification.