לוח משרות דרושים חשמל ואלקטרוניקה בתל אביב יפו

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.

What you'll be doing:

Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.

Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.

Define the implementation of debug capabilities to support performance validation and improvements

Understand our system requirement and help define the POR of our switch product line.

Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.

Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.

Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

We are looking for a 100% hands-on Storage Services Software engineer to join the block storage group. You will be a member of a team that builds the next generation block storage capabilities. You will work closely with a variety of teams and architects including the networking team, and external customers. You will take part in defining the software architecture and implementation of the most advanced storage services! Services that will need to meet extreme performance and scalability demands! We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.

We work, think and learn as a team. We thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. The rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.

What youll be doing:

100% hands-on coding role in C language, kernel and userspace.

Research, design, implement and test, new and existing, networking features for distributed storage services and features of our block storage solution, in both Host and DPU environments.

Acquire understanding of the algorithms, the technicalities and the interaction with other components across our block storage ecosystem.

Analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox kernel modules and often in other components. Drive new solutions based on any issues that arise.

We are searching for a forward-thinking Software Engineer to join our VLSI Design Automation Infrastructure team. We are looking for a candidate who looks beyond traditional scripting and is eager to leverage Artificial Intelligence and Machine Learning to revolutionize how we build chips.

In this role, you will manage high-performance compute and storage environments while pioneering the integration of AI-driven tools into our workflows. You wont just maintain the infrastructure; you will modernize it-using LLMs to optimize code, ML to predict compute bottlenecks, and intelligent automation to streamline the backend networking team's success.

What youll be doing:

AI-Driven Optimization: Leverage AI/ML methodologies to analyze compute and storage patterns, predicting resource needs and optimizing LSF grid performance.

Next-Gen Tooling: Design and develop intelligent scripts and automation tools, integrating Generative AI (LLMs) to accelerate debugging and workflow generation.

Infrastructure Management: oversee complex On-Prem environments (LSF) and storage solutions, ensuring maximum uptime for critical VLSI projects.

Data Visualization: Build dynamic, data-driven dashboards that not only report status but utilize analytics to provide actionable insights on infrastructure health.

We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.

As a Senior Chip Design Verification Engineer in the DFT team, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

Our networking VLSI team is looking for a CAD engineering manager. The team is providing methodologies and vendor-based EDA flows for the physical design execution teams. Your team will be responsible for defining and developing methodologies and flows that enable high quality and super-efficient execution of over a hundred physical design engineers. You will be working closely with the physical design technology team, with design engineering professionals and project leads, and with peer software/CAD teams, hence you will need to possess strong interpersonal skills, be a quick learner, and manage multiple missions in a results-oriented manner. You, along with the team, will lead processes from requirements understanding, through software definition and implementation of tools/flows, ending with release, integration and support.

What you'll be doing:

Lead a growing team of ~5 professional CAD engineers.

Own the definition, development, and maintenance of software solutions for physical design engineering.

Collaborate and closely interact with design technology experts and execution engineers, along with software/CAD peers.

Influence and make right choices to produce high quality and tangible impact.

Be agile and make continuous and incremental progress by decomposing the problem in to smaller and achievable goals.

Define and build strategic vision for the networking VLSI technology and EDA team.

We are at the forefront of AI-driven innovation in VLSI design automation. Join us to shape the future of semiconductor design with cutting-edge AI tools and make a significant impact in a collaborative, high-performance environment. Are you ready to push the boundaries of whats possible in VLSI CAD? Come be part of our pioneering team!

What you'll be doing:
You will be responsible for developing and integrating advanced CAD solutions and automation flows using AI and machine learning for VLSI design, verification, and implementation.
Work closely with design, verification, and CAD teams to identify areas for improving VLSI workflows using advanced tools and methods.
Research, prototype, and deploy AI-based algorithms.
Develop and maintain scripts and automation infrastructure to enable seamless adoption of AI tools in the VLSI design process.
Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date.
Provide technical support and training to engineering teams on AI-enabled CAD flows and best practices.

We are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

We are seeking a Networking Software Engineer to join our RDMA Transport Software team, driving the development of next-generation RDMA solutions for AI, cloud, HPC, and storage. You will research and develop innovative transport algorithms that push the limits of performance and scalability. You will work in a fast-paced, collaborative environment alongside talented engineers from around the world, supporting the data needs of the worlds largest enterprises

What you'll be doing:
Take part in research, design, and development of advanced RDMA transport mechanisms and algorithms, enhancing performance, reliability, and scalability.
Collaborate closely with hardware engineers, software developers, and system architects to align on project objectives and requirements.
Keep up with industry trends and emerging technologies, integrating new ideas and innovations into the development process.

We are seeking a System Software Validation Lead to define validation methodologies, set quality standards, and drive a culture of quality across multidisciplinary hardware and software systems. This leadership role emphasizes process ownership, methodology enforcement, and coaching teams, while also providing technical guidance and hands-on validation expertise.
Responsibilities:
Define and enforce validation methodologies, processes, and quality standards across firmware and embedded software.
Lead validation planning and execution reviews, ensuring coverage, consistency, and defect prevention.
Establish automation and CI/CD validation strategies and guide adoption across teams.
Mentor and coach engineers to embed quality practices and foster continuous improvement.
Provide technical leadership in system-level validation, including algorithms and machine learning within firmware and embedded software environments.
Oversee validation execution on ATE platforms, ensuring correlation between simulation, emulation, and silicon test results.
Accountable for high-level analysis of production issues, driving defect escape reviews, enhancing test coverage, and defining quality gates to enforce continuous improvement.

Our Networking System Validation Group is growing, and we are hiring a Junior Switch System Validation Engineer. As a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. You'll gain networking and Switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like Quality-of-Service, performance, logic correctness, and AI features.

You will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages.

You should have a good grasp of software development in different fields, such as Python Scripting, embedded software, and device firmware. It's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans.

 
What you will be doing:

Work in a combined design and verification team specializing in Switch Full Chip works.

Understand the Switch architecture and build on test plan accordingly.

Develop Full Chip test collaterals/suites, maintain regressions, debug failures and sign-off coverages.

Maintain test suites to facility Emulation and/or Silicon platforms checkout as well.

We are now looking for a Senior verification manager for our FC Switch Silicon team. As a FullChip verification manager in NVIDIA's Networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a FC team, responsible to integrate and verify the Switch at system level.
Lead and grow a team of FullChip verification engineers.
Responsible to drive the FullChip verification execution, including staging plan of the projects and deliveries.
Provide technical guidance, mentoring, and support to engineers in the team.
Work closely with multiple teams within organizations such as Architecture, u-arch, Full chip Micro-Architecture, BE, and FW.
Dynamic verification environments planning for units infrastructures and system level.
Work with design/verification team which develops core units within the Switch silicon.

In this role, you'll guide a team of experienced engineers and team leads, coordinating execution across multiple product lines. You'll have a direct impact on our networking products-from VR72 to next-generation AI fabric solutions-and play a key role in scaling our capabilities while pioneering AI-enhanced workflows.

What you'll be doing:

Guide day-to-day execution across multiple concurrent product lines, with ownership of firmware debug and validation delivery.

Mentor and develop team leads (currently 3 direct reports), helping them grow their technical and leadership capabilities while thoughtfully allocating resources across priorities.

Collaborate with teams across Chip Design, Software, Architecture, QA, and Applications to solve technical challenges together.

Encourage AI adoption and explore AI-enhanced workflows that improve team effectiveness.

Help translate customer needs into meaningful product improvements.