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חברה חסויה
Job Type: Full Time and Hybrid work
Excellent written and oral communication skills
Implement the video pre/post-processing algorithms using FPGAs tools and procedures
Define and coordinate interfaces within the system
Define TEST procedures for overall FPGA Design
Requirements:
lectrical Engineering Science degree (B.Sc.)
At least 5 years hands-on experience with FPGA design
Knowledge in SystemVerilog RTL coding
Familiar with scripts languages - PERL / Bash / Python / TCL
High motivation, be self-driven and be able to work as a Team player and also perform independent tasks
This position is open to all candidates.
 
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21/04/2025
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Digital Group leader to grow our Digital team, who would lead design and verification activities and be involved with a variety of research, architecture and integration aspects.

Your Day to Day
Lead and manage a dynamic group of digital design and verification engineers focused on developing innovative image sensors and ISP solutions.
Define and prioritize project objectives, timelines, and deliverables to align with our companys strategic goals.
Oversee the design and verification process of ASIC and FPGA projects through system integration to our innovative image sensing solutions.
Collaborate closely with cross-functional teams, including analog design, firmware, and software engineers, to ensure seamless product integration and performance.
Analyze and optimize digital signal processing algorithms and FPGA implementations to enhance image quality and sensor performance.
Mentor and provide technical guidance to your team members, fostering a culture of growth and innovation.
Requirements:
You hold a Bachelors degree in Electrical Engineering, Computer Engineering, or a related field, with a Masters degree being a plus.
You have 10 years of hands-on experience in design and verification of ASIC/FPGA and mixed signal systems, particularly in the realm of image sensors or closely related technologies.
You have at least 5-7 years of experience in a leadership or managerial role.
You possess a solid background in ASIC/FPGA development, including experience with HDL coding, verification methodologies such as UVM, backend and system interfaces.
You are proficient with common industry digital design tools and simulation software, such as Cadence/Synopsys, and FPGA environments Xilinx/Intel.
Your excellent leadership, communication, and project management skills empower you to thrive in a fast-paced, collaborative environment.
You are adept at managing multiple projects simultaneously, ensuring timely and high-quality deliverables.
An advantage - expertise in embedded systems and firmware development, as well as knowledge of Backend flow, manufacturing processes, and design for test (DFT) methodologies.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data centers.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience with RTL development for ASIC subsystems using Verilog.
Experience with speed interfaces such as PCIe, InfiniBand, and their low latency, security, and reliability principles.
Experience with micro architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience with scripting languages (e.g., Python or Perl).
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Knowledge of high performance and low power design techniques.
Knowledge of FPGA, emulation platforms, and SoC architecture.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools on Emulation and/or FPGA platforms.
Lead the debugging and resolution of complex silicon issues, collaborating with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.
Build and mentor a high-performing team of silicon validation engineers, fostering a culture of collaboration, innovation, and technical excellence.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
8 years of experience in silicon validation or a related field.
Experience in leading technical teams and build cross-functional relationships.
Experience in silicon validation methodologies, tools, and techniques, including hardware setups, and automation tools on Emulation or FPGA platforms.

Preferred qualifications:
Experience with Field-Programmable Gate Array (FPGA) prototyping, Hardware Emulation (ZeBu Server, Palladium, Veloce), or simulation platforms.
Knowledge of cloud computing technologies and architectures, including data centers, networking, and storage.
Familiarity with hardware description languages (e.g., Verilog, VHDL) and hardware verification methodologies (e.g., UVM, SystemVerilog).
Excellent communication skills, with the ability to convey technical concepts to diverse audiences.
This position is open to all candidates.
 
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16/04/2025
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a highly experienced Logic Design Engineer who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding experienced DevOps Engineer customer base.

Join us in this exciting journey to redefine the future of quantum computing.

Responsibilities:

Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Requirements:
BSc in electrical/computer engineering or relevant military background- Must
At least 7 years of experience- Must
Proven track record in RTL coding with System Verilog- Must
Experience with System Verilog- Must
VCS, Vivado - Advantage
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Define and implement solutions for complex design, integration and verification problems using in house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Be involved in project development and convergence with the highest quality, work on issues as they arise through design and implementation.
Connect between RTL design, physical design, DFT, external IPs and System on a Chip (SoC) while maintaining project priorities.
Maintain project infrastructure and stability.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
Experience with design from micro-architecture through implementation with Verilog/SystemVerilog, or VHDL language.
Scripting experience.

Preferred qualifications:
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation).
Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
Ability to muti-task, and have a can-do approach.
Excellent communication and facilitation skills.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
Participate in evaluation of future ASIC designs and general architecture for executing data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications
Define efficient micro-architecture and block partitioning/interfaces and flows
Requirements:
Bachelor's degree or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience working with design networking such as RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in a procedural programming language (e.g., C++, Python, Go).
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
Plan the verification of digital design blocks by understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with Strategic Value Add (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
5 years of experience verifying digital reasoning at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASIC.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Experience in verifying digital systems using standard Internet Protocol (IP) components or interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in estimating performance by analysis, modeling, and network simulation in defining and driving performance test plans.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with ASIC standard interfaces and memory system architecture.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
Contribute to CPU front-end designs, emphasizing micro-architecture and RTL design for next generation CPU.
Propose performance enhancing micro-architecture features with efficiency in mind. Work with architects and performance teams for trade-off studies.
Deliver designs that meet power, performance, and area (PPA) goals with production quality.
Interpret techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with CPU microarchitecture.

Preferred qualifications:
Experience in scripting languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SoC level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.).
Experience in reasoning design and debug with Design Verification (DV).

Preferred qualifications:
Experience in coding languages like Python or Perl.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of System-on-a-Chip (SoC) architecture.
Knowledge of PCIe, UCIe, DDR, AXI or ARM processors.
This position is open to all candidates.
 
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