we are hiring a senior, hands-on engineer to lead technical innovation in our Design Verification (DV) automation infrastructure. This role requires a strong design/verification background combined with a proactive approach identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. You will directly influence how verification is performed across our companys next-generation Networking chips, enabling more scalable, efficient, and robust flows for complex ASICs powering the AI revolution.
What you'll be doing:
Lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
Identify key challenges and inefficiencies in current DV methodologies and proactively propose and implement improvements.
Work closely with DV engineers, design teams, and tool developers to ensure solutions are practical and impactful.
Balance innovation with hands-on engagement in daily DV issues keeping a strong connection to real-world challenges and support needs.
Act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for DV automation.
Requirements: B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering (or related field).
5+ years of experience in Design Verification/Chip Design, with a deep understanding of simulation, testbenches, regression infrastructure, and debug.
Proven ability to identify inefficiencies or recurring issues in DV workflows and develop automation scripts or tools to streamline processes and improve efficiency.
Strong analytical thinking and problem-solving skills.
Proficiency in Python and Linux.
Excellent communication and collaboration skills comfortable working across engineering teams.
Ways to stand out from the crowd:
Experience with contemporary DV methodologies, such as intelligent test planning or advanced debug workflows (e.g., automated log parsing, waveform analysis, or triage tooling).
Familiarity with recent industry trends in design verification, including AI-assisted debugging, smart triage, or LLM-based tools.
Proven ability to craft and deliver custom automation flows that scale to large regressions or complex simulation environments.
Hands-on contribution to DV infrastructure development within CAD/DA teams or large SoC projects.
Comfort working across teams, collecting feedback, and turning it into practical, adopted tooling.
This position is open to all candidates.