לוח משרות דרושים ASIC / VLSI משרה מלאה

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance of every detail?
Come join our growing wireless silicon development team!
As part of our Silicon Technologies group, youll help design our next-generation, power-efficient, system-on-chip (SoC). Our wireless SoC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level. Joining this group means youll be responsible for crafting and building the technology that fuels our devices. Together, you and your team will enable our customers to do all the things they love with their devices.

If you enjoy a fast-paced and challenging environment, and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.

Responsibility of block and/or sub-system micro-architecture and design implementation.
Work with architects and system teams to define the right solution for the product requirements.
Implement block and/or sub-system design, analyze performance and power and support verification teams.
Responsibility of FE flows such as synthesis, CDC, RDC and Lint to ensure high quality production worthy design.

As a PNR/PD-CAD team member, you will have an impact on a wide range of activities and domains in the PD world. The team develops and supports utilities that enable an efficient work environment for the physical design teams across the world.

The role includes exploring new technologies and methodologies of first-of-its-kind designs, and the complex implementation of designs from small ones to the largest possible.
The job includes hands-on work and impact on all aspects of the design cycle, from infrastructure-related automation for design efficiency through developing internal PNR flows, which will enable improved designs - from PNR implementation through developing infra, signoff flows & verification utilities.

Responsibilities:
The job includes constant work with different teams and disciplines that interface with the PNR world, which includes Timing, power delivery, synthesis, Physical Verification, and more.
Along with the different disciplines, you will work with different teams, from vendors, PD team members and other CAD team members and discipline owners across the world to enable and improve the productivity of the PD flows.

We are seeking an experienced ASIC AI/ML Engineer with deep expertise in AI/ML infrastructure and application development specifically for semiconductor design verification disciplines. The ideal candidate will have a proven track record of delivering end-to-end AI solutions from concept to large-scale production deployment.
In this role, you will collaborate directly with architects, designers, verification engineers, software teams, and backend specialists to define best practices and deploy production-ready AI-driven workflows and applications. Your focus will be on implementing LLM, GenAI, and classical ML solutions that transform our ASIC design verification processes and accelerate our path to tape-out.
Key job responsibilities
Develop and maintain scalable AI/ML infrastructure for ASIC design and verification teams
Architect, develop, and deploy production-ready AI/ML applications for semiconductor design workflows
Design and implement GenAI solutions including LLMs and agentic AI systems for verification processes Invent innovative AI-driven solutions to eliminate identified inefficiencies in design and verification flows
Establish best practices and standards for AI/ML application development in semiconductor environments
Create monitoring and observability frameworks for AI model performance in production design environments
Collaborate cross-functionally with architects, designers, verification engineers, and software teams
Research and evaluate emerging AI technologies for applicability to semiconductor design challenges.

we are looking for a Experienced Verification Team Leader - FPGA/ASIC.
Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.
Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station.
Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

Were hiring an experienced verification engineer to join our team developing advanced telecommunications ASIC/FPGA products.
You will join family, as part of our team in Beer-Sheva.
Responsibilities:
Build and maintain verification environments (SystemVerilog/UVM or Specman)
Develop test plans and run constrained-random & directed tests
Debug, analyze coverage, and work closely with design teams
Contribute to methodology and process improvements

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

we are looking for a Senior Hardware Architect for Mobile broadband.
As a senior architect you will be a leader, someone who brings into the company new ideas and helps drive next generation wireless products
Responsibilities:
Be a leader in the Mobile Broadband team, architecting state-of-the-art modems for next generation cellular solutions. Investigate, invent, develop, innovate wireless modem components. Drive the implementation phase with the VLSI, Software and Algorithm teams.

we are looking for a Senior VLSI Design Engineer.
As a Senior VLSI Designer, youll lead the full design flow of advanced DSP cores and accelerator- from architecture to timing closure. This hands-on role is key to developing the IPs behind the next-generation products, with strong cross-functional collaboration and technical ownership.
Responsibilities:
As a Senior VLSI Designer, you will be responsible for the end-to-end design and implementation of advanced digital IPs, including DSP cores and hardware accelerators. You will work across the full design flow- from architecture definition and micro-architecture design, through RTL development and verification, to synthesis, timing closure, and static timing analysis (STA). Your work will directly contribute to the silicon success of next-generation products across various domains.

We are seeking a highly skilled and motivated VLSI Backend Team Leader to join and lead our dynamic team.
As part of this position, you will lead a team of experienced engineers working on parallel projects, and play a crucial role in the design and implementation of complex designs, flow development, and the latest technology node bring-up and integration.
The Backend team leader will be required to do 50% hands on work and 50% managerial work.

Power the Future with us! We are a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery Storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. We are a top global leader in smart energy technology. The company's broad range of products encompasses intelligent inverter and Storage systems, revolutionary EV charger, smart energy management solutions and more. Our ASIC controllers stand at the heart of the companys innovation, being both highly flexible and low power, combining digital logic with analog circuits design. At SolarEdge, HW engineers, SW developers and ASIC engineers work together in close collaboration to bring to life a complete solution for the solar energy market. We are looking for an ASIC Digital Design Engineer that is eager to learn and be part of a succeeding team.
What you will be doing:
* Take part in the design of complex mixed-signal devices.
* Collaborate with digital design and Verification engineers in developing digital IPs.
* Work closely with power engineers and SW developers to achieve a deep system understanding.
* Learn how to integrate analog IPs into a digital device.
* Work in a diverse and enriching environment.
Country:
Israel
City:
Herzliya

Power the Future with us! SolarEdge (NASDAQ: SEDG), is a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. We are seeking a passionate and detail-oriented Student to join our team and contribute to post-silicon validation activities for ASIC devices. This role offers a unique opportunity to deepen your expertise in analog and mixed-signal circuit characterization and contribute to cutting-edge semiconductor development. Responsibilities
* Perform lab characterization of mixed-signal and analog IPs including ADCs, DACs, voltage references (Bandgap), sensing amplifiers, and analog channels
* Analyze measurement data using tools such as Excel and MATLAB, and compare results against specifications
* Develop and document technical reports and measurement procedures
* Implement test automation through coding
* Troubleshoot lab issues and resolve bugs by applying deep analog circuit knowledge
* Collaborate closely with the design team to support validation efforts

Country:
Israel

City:
Herzliya

Join our Networking Silicon team as a Senior Full-Chip ASIC Engineer. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level. You will contribute to the architecture of high-speed communication devices by building advanced simulation platforms and driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers.

What youll be doing:
Full-Chip Verification & Execution: Own complex system-level features by defining verification plans and driving the end-to-end execution.
Software Simulation Development: Architect and code robust software simulation platforms that serve as the foundation for Firmware development and uArchitectural research
AI-Enhanced Engineering: Accelerate development by leveraging cutting-edge AI coding tools and frameworks.
Global Technical Collaboration: Partner with Architecture, FW, and SW engineering teams across the globe to deliver industry-leading networking solutions

We are looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASIC-from initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles.
Responsibilities:
Own and lead the end-to-end ASIC development process.
Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
Define and enforce VLSI development methodologies, design flows, and quality standards.
Evaluate and select both digital and analog IPs required for the ASIC.
Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.