לוח משרות דרושים ASIC / VLSI משרה מלאה

We are on the lookout for a dedicated and driven Software Engineer to join our dynamic VLSI Design Automation team. This team focuses on the development of VLSI CAD tools and web applications, and is responsible for managing and maintaining high-quality VLSI infrastructure, including compute and storage for the Backend Networking team. We seek a passionate engineer eager to effectively manage compute and storage, develop scripts, automate processes, and create dashboards and applications. Our ideal candidate is someone with experience in VLSI methodologies, data-driven, eager to learn, and possesses strong interpersonal skills.

What youll be doing:

Oversee and optimize compute and storage resources, ensuring operational efficiency and success of VLSI projects. Develop and maintain scripts and automation tools to streamline infrastructure tasks.

Engaging in the entire lifecycle of tool and web application development, which includes backend, frontend, data storage design, UI/UX design, testing, deployment, and maintenance.

Design, implement, and maintain dashboards for monitoring and reporting on infrastructure performance and usage.

Challenge existing VLSI methodologies to have better tools and flows.

We are looking for a talented and driven VLSI CAD Automation & DevOps Engineer to join our team. This role combines expertise in front-end automation, continuous integration, CAD tooling, and full-stack development to support and enhance our VLSI verification workflows.
What will your job look like:
Flow & CI/CD Automation
Automate RTL lint, CDC/RDC, synthesis checks (front‑end only), and UVM regression flows.
Build and maintain CI/CD pipelines (Jenkins/GitLab CI) for simulation, coverage collection, and sign‑off checks.
Implement pre‑submit checks (lint, CDC) and nightly regressions with dashboards for pass/fail and coverage metrics.
EDA Tooling & CAD Enablement
Manage and integrate front‑end EDA tools (e.g., VCS, Xcelium, Questa, SpyGlass).Develop scripts to parse logs/reports (lint, CDC, coverage, simulation) and generate actionable summaries.
Maintain PDK-independent front‑end tool configurations and flow reproducibility.
Compute & Licensing
Operate and optimize compute farm schedulers (LSF/SLURM/Grid Engine) for simulation and regression jobs.
Monitor and tune license usage for front‑end tools (FlexLM/Lmx), ensuring high availability and efficiency.
Observability & Support
Build dashboards for regression health, coverage trends, and farm/license utilization.
Troubleshoot flow failures, triage environment vs. design issues, and publish runbooks for common problems.

Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.

Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

Our Automated Driving group in Haifa is looking for a Junior DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.

At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Our Automated Driving group in Haifa is looking for an experienced SoC Design Engineer for DFT team.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Our Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

Required VLSI Logic Design Technical Lead
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

Our Imaging Radar group develops innovative high-performance Radar solutions for ADAS and Autonomous Driving markets.
We are seeking an experienced SoC Architect to join us.
What will your job look like:
Lead End-to-end life cycle of the Radar System-on-Chip architecture definition and development.
Provide detailed specifications for chip modules and flows.
Work in close collaboration with the various teams, including system, algo, design, verification, backend, firmware, package and post-silicon.

Required Experienced Logic Design Engineer
The EyeC VLSI team specializes in designing advanced radar system chips for ADAS (Advanced Driver Assistance Systems) and autonomous vehicles. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.
What will your job look like:
Design ownership on major blocks/clusters from definition to implementation phase.
Participate in various ASIC activities and flow definition which includes CDC, DFT, Lint.
Design micro-architecture of custom blocks.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

Power the Future with us! a global leader in high-performance smart energy technology, with over 3000 employees, offices in 33 countries, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery Storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive. We are looking for an experienced Analog Design Group Manager to lead and grow our analog design team. The ideal candidate will have deep expertise in complex analog circuit design, including ADCs, acquisition systems, and power management, as well as proven leadership in managing design teams and delivering successful silicon tape-outs. What will you be doing: Lead and mentor a team of analog design engineers in the development of complex mixed-signal and analog ICs.
* Drive architecture, specification, and implementation of analog blocks such as ADCs, acquisition systems, and power circuits.
* Oversee the full design cycle from concept through to tape-out, ensuring high-quality results (including DRC/LVS sign-off).
* Collaborate closely with digital design, verification, layout, and system engineering teams.
* Define methodologies, best practices, and quality standards for analog design within the group.
* Provide technical guidance, training, and career development for team members.

Be part of a dynamic and motivated modem VLSI design team. Take part in a complex SOC VLSI chip-design activities with major focus on advanced digital signal processing and modem subsystem development, covering architectural, front-end design, verification and physical-design aspects.
 Responsibilities
VLSI development of digital modules from concept to final implementation, meeting physical design entry requirements.
Be part of a multi-team developing advanced signal processing cores and subsystem solution.
In charge of adjusting, deploying and integrating the subsystem into company design environment.

We are looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
You'll be responsible of architecture of the DFT solutions across the SOC (MBIST, SCAN ATPG, LBIST and more)
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts as it required by the Automotive and Safety related products market (ISO26262).

We are looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASICfrom initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles.

Responsibilities:
Own and lead the end-to-end ASIC development process.
Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
Define and enforce VLSI development methodologies, design flows, and quality standards.
Evaluate and select both digital and analog IPs required for the ASIC.
Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.