דרושים » חשמל ואלקטרוניקה » VLSI Design and Micro-Architecture Engineer

we are now looking for hardware senior manager for our hardware switch group! the team leads the development of networking infrastructure for nvidia next-generation data centers focusing on accelerated performance while enabling optimized end to end gpu connectivity. as a leader to our hardware engineering team, you'll guide, encourage, and drive a team of highly knowledgeable hardware engineers, providing them with interesting and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.
what you'll be doing:
build the best team to implement and executing high-performance systems
a key member of team technical management team developing world-class switch designs
lead pioneering switch system design from concept to mass production
collaborate and integrate with all hw project disciplines: board design, mechanics, thermal, pcb layout, production, software/firmware, rtl and more
planning the work of your team on multiple simultaneous development projects with a broader leadership team
managing direct reports, goal setting, coaching, performance appraisals, career planning and compensation recommendations
schedule projects, make realistic estimates of outcomes and work to make projects timely and successful for high volume manufacture.
this position is very hands-on and will require you to be intimately familiar with the entire design flow. from a technical standpoint, you will be hands-on and driving the engineering teams working the following parts of the project: specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes, micro-architecture, verification, characterization, design for testability, cost,reliability and more.

we are now looking for a chip design Verification engineer to join the chip design methodologies team. the team is in charge of the verification methodologies, shared code, training, and embracing new technologies. one of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. this position offers the opportunity to have real impact in a dynamic, technology-focused company.
what you'll be doing:
develop shared verification code and solutions to be widely used by the chip design team.
develop groundbreaking methodologies to create a flawless experience for Verification engineers to keep the focus on new problems.
collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
get in touch with eda vendors to learn about cutting-edge tools/technology and apply them into our verification process.
understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
collaborate with designers, verification specialists to accomplish your tasks.
develop training sessions.

we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use the asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.the ml, systems, & cloud ai (msca) organization  designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the design activities at ips, subsystems(s.s) and SOC.
plan, execute, track progress, assure quality, report status of the assigned activity.
lead a team of designers both directly and in teams.
define the block/ SOC level design documents such as micro architectural specifications.
own ip, s, SOC strategies for clocks, resets, and debugs. enforce global methodologies and drive enhancements.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
lead the end-to-end execution, tracking, and convergence of chip-level cdc and rdc for complex socs across all ips and partitions.
plan and orchestrate cdc/rdc signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
run and maintain cdc/rdc flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
triage violations efficiently: root-cause to rtl, constraints, tool setup, or ip models; prioritize and drive fixes to closure with owners.
verify reset architecture and rdc robustness (reset domain intent, release sequencing, glitch detection, fanout).
author and review cdc/rdc constraints, waivers, and justifications; ensure auditability and signoff quality.
automate runs, report parsing, dashboards, and kpis for closure tracking using scripting and data tooling.
partner with rtl, dv, dft, sta, pd, and architecture to align fixes, manage ecos, and protect cdc/rdc quality during late design changes.
define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
continually improve methodology and training to prevent recurring cdc/rdc issues and accelerate convergence.

* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.