לוח משרות דרושים ASIC / VLSI, לחיפוש זה נמצאו 33 משרות

We are rebuilding the way chips get built, and were looking for a senior engineer to help lead that transformation.

This is a full-stack platform role on the team responsible for the development environment behind our silicon. You will help define how agentic orchestration and durable execution become first-class parts of the chip-design workflow.

Were looking for someone who has built complex systems before - across backend, frontend, and infrastructure - and is ready to set the technical direction for what comes next.

What You'll be doing:

Architect and lead full-stack EDA platforms end to end, from data models and backend services to the frontends engineers use every day - while making key technical and build-vs-buy decisions.

Own the infrastructure these platforms run on at scale, including CI/CD, containerization, observability, on-prem compute, and cloud-native Kubernetes environments.

Set engineering standards across the team by leading design reviews, improving reliability and developer experience, and mentoring engineers.

Act as a technical leader across silicon, backend, and design-automation teams, helping turn fragile manual flows into dependable automated systems used by many engineers.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions.
About us
The company has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on advanced, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture

our company's Automated Driving group in Haifa is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting edge technologies - Autonomous Vehicle (AV) SoC.
At our company's Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules
Verify and Validate our design
Debug and analyze coverage and yield loss
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

Scd is Hiring Mixed-Signal Test & Validation Engineer (IR ROIC) Job Description: We are looking for a hands-on Test & Validation (post silicon) Engineer to join our VLSI design group, focusing on Infrared Readout Integrated Circuits (IR ROICs).
This role sits at the intersection of circuit design, silicon validation, and system-level characterization. You will work closely with analog and mixed-signal designers to ensure testability is built into the design from early stages, and later take ownership of silicon bring-up, validation, and electro-optical characterization.
Responsibilities: • Define and drive DfT for analog/mixed-signal: observability, controllability, test modes, and measurement access • Contribute in design/layout reviews to ensure testability; define validation strategy pre–tape-out • Lead first silicon bring-up; execute block and full-chip validation; debug with design teams • Plan and run characterization across PVT and modes; analyze noise, linearity, DR; correlate sim ? silicon • Collaborate with Physics/System teams on electro-optical and radiometric performance of the hybridized ROIC • Build and maintain lab setups; develop automation (Python) for data acquisition and analysis; document methods/results • Perform failure analysis and debug issues to identify root causes and implement corrective actions. • Document test results, methodologies, and procedures for future reference. • Stay updated with the latest advancements in VLSI testing technologies and methodologies.

Designs and develops integrated circuits. Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.
- Knowledge: Having wide-ranging experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways.
Strong project management skills
Leads design and delivery of new
products/process
Functional breadth and depth, plus expert in complementary fields
Applies broad concepts and theories to achieve innovative and effective solutions to complex problems - Job Complexity / Contribution : Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors. Exercises judgment in selecting methods, techniques and evaluation criteria for obtaining results. Networks with key contacts outside own area of expertise.
Will champion significant projects, programs and business initiatives using demonstrated creativity and ingenuity
Team leader
Leads major projects
Influences or impacts others'
priorities, decisions or activities
Escalation point for complex issues
Coaches and mentors other junior team members - Supervision : Incumbents provide a leadership role for the work group through knowledge in his/her area of specialization. Generally free to determine work priorities based on general direction from managers.
Determines methods and procedures on new assignments
Consults with management on long-range goals
Determines own priorities, both tactical and strategic

We are seeking a highly skilled and motivated VLSI Backend Team Leader to join and lead our dynamic team.
As part of this position, you will lead a team of experienced engineers working on parallel projects, and play a crucial role in the design and implementation of complex designs, flow development, and the latest technology node bring-up and integration.
The Backend team leader will be required to do 50% hands on work and 50% managerial work.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company.
Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

We are looking for highly motivated engineers who love the challenges and the opportunity of a small company.
Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing.
Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

we are looking to hire a talented VLSI DFT Engineer to join our VLSI group in Tel Aviv. You will work alongside other talented engineers to develop our cutting edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Develop and deliver production test patterns (ATPG), including stabilization, coverage analysis, and debug
Analyze silicon failures and drive debug across DFT, design, and test flows
Collaborate with design teams to implement and optimize unique DFT architecture and methodologies (scan, MBIST, etc.)
Participate in pre-silicon verification of DFT features and flows
Contribute to end-to-end DFT flow, from implementation through silicon bring-up

we are looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
Define, track, and close functional and performance coverage to guarantee verification completeness.
Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.

we are looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Bring architecture requirements of AI Chips to a power and area efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with backend and DFT to converge the design into silicon.
Join the bring up of the features with SW when silicon is back in lab and the magic happens.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities:
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities:
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.