לוח משרות דרושים ASIC / VLSI

Our EYEQ VLSI team is looking for an ASIC design engineer to be involved in the development of our current and future SoC. Working on the cutting-edge technologies to deliver our EyeQ SoC family for ADAS and autonomous vehicles.
What will your job look like:
You will work on developing the next generation of our SoC for ADAS and AV.
Be involved in deep understanding of the design at multiple levels: the micro-architecture, features and specification.
Design and implement new proprietary IPs and system features.
Integrate third parties and proprietary IPs in a multi-clock domain system on chip.
Verification, synthesis, static timing analysis, and closure.
Power and Area Optimizations.
You will become familiar with design environment, flow, tools, methodologies and optimization methods
Collaborate with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

Innoviz Technologies is looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASIC—from initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles. Responsibilities
* Own and lead the end-to-end ASIC development process.
* Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
* Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
* Define and enforce VLSI development methodologies, design flows, and quality standards.
* Evaluate and select both digital and analog IPs required for the ASIC.
* Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.

Sub Department:
VLSI

City:
Rosh Ha‘Ayin

we are seeking a highly skilled and motivated Field Service Engineer to be based in our Israel office. This role is primarily dedicated to supporting systems located facility, while also providing additional support during peak demand periods at customer sites. The successful candidate will be responsible for maintaining and reconfiguring test systems and probers, supporting device program development, overseeing facility equipment, and coordinating with external vendors.


Key Responsibilities

Maintain and reconfigure Teradyne office-based systems and probers in alignment with device program development requirements.
Supervise facility equipment and coordinate vendor support for maintenance and repairs.
Provide technical assistance to customers and field teams, both on-site and remotely (via phone or email).
Install and upgrade test systems, including hardware options and software updates.
Diagnose and repair system issues at both Teradyne facilities and customer locations.
Be available for frequent travel, including international assignments, on short notice.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

We are in the early stages of a new project and looking for a talented Senior engineer to take on a key role, leading Verification efforts of major parts of our ASIC - from scratch

Roles and responsibilities:
Take ownership of Verification for large ASIC clusters.
Plan, build, and execute the Verification environment end-to-end.
Mentor and guide juniors/students.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities:
Join a team of VLSI frontend design engineers in Chain-Reactions projects.
Define, plan and implement our next chip in Chain-Reactions on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

we are a global leader in quantum computing control systems. Through our pioneering hardware and software solutions based on instruction-based quantum control, we're revolutionizing how quantum computers are built and controlled. As we stand at the forefront of exponential growth in quantum computing, we're assembling an elite team that actively shapes the evolution of quantum technologies.
We are seeking an exceptional architect to join our Architecture team and help shape the future of quantum computing. As quantum computers near production scale, were uniquely positioned to define the system and software architecture that will power the next generation of computing.
In this role, you will be responsible for end-to-end definition of new capabilities, from the quantum programming languages through the compilation processes to the pulse processor. This position demands deep expertise in software architecture across all levels, an ability to work closely with logic design teams, a strong ability to learn and adapt, and a passion for becoming an expert in quantum computing. Youll collaborate closely with Product, R&D, and Research teams to transform ideas into technical reality.
Responsibilities
Design quantum control programming languages and representations optimized for our unique hardware and application requirements
Define architecture in our unique pulse processor end-to-end, from language and software interface to logic capabilities
Define system-level architecture and features, and provide comprehensive specifications for R&D implementation
Collaborate cross-functionally across Software, Compiler, Logic Design, and Quantum Software teamsfrom concept to production
Work hand-in-hand with Product and Research teams to translate high-level requirements into concrete architecture plans
Development of Proof-of-Concepts for new software capabilities and features.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
You will also be responsible for performance analysis for a networking stack.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customes, Cloud customers and the billions of people who use our companyservices around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing ASICs used to accelerate networking in data centers. You will have dynamic, multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
You will be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our server chip design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Technical Leadership and mentor team members.
Communicate and work with multi-disciplined and multi-site teams.

Join the our team in developing a unified silicon architecture for web-scale and service provider networks.
our team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact
Define devices and deliver specifications to other development teams.
Work with internal and external customers to understand and define current and future requirements.
Innovate at all levels to deliver market-first features and solutions.
Conduct in-depth research to shape the architecture of next-generation networking devices.
Contribute to full-chip integration and cross-functional collaborations to enhance design methodology.
Participate in the definition and analysis of networking system solutions, ensuring they meet market and technical needs.

You'll join our architecture team, central to silicon development.
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specification.

You'll join our architecture team, central to silicon development .
You will define features of future devices using the latest silicon technologies, focusing on Logic Design and coding.
You will be responsible for defining the device specificaton.