לוח משרות דרושים ASIC / VLSI

As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.

Responsibilities:

Understanding the high-level specification and requirements of functional units of micro-controller and application processor products.

Define the Micro-architecture for an unit and developing its RTL, including all design stages.

Collaborate with verification team on the test plan development for the blocks and verification closure.

Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets.

We are looking for an experienced and creative AI processor VLSI Architect to architect and model the core of our next generation processors.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Responsibilities:
We offer the opportunity to join our growing frontend design team.
Join a team of VLSI frontend design engineers in Chain-Reactions projects.
Define, plan and implement our next chip in Chain-Reactions on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

We are looking for a talented VLSI Verification Engineer to join our team.

In this role, you will work on verifying complex ASIC designs, and collaborating with cross-functional teams to ensure silicon success.

You will define and implement verification strategies, debug failures, and contribute to the quality of our next-generation products.

Key Responsibilities:
Define verification plans and environment micro-architecture.
Implement UVM-based verification environments.
Debug and analyze failures at various stages of verification.
Develop coverage models and metrics to assess design readiness.
Support cross-functional teams (Analog, Backend, Production, etc.) on verification-related challenges.

We are looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASICfrom initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles. Responsibilities
* Own and lead the end-to-end ASIC development process.
* Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
* Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
* Define and enforce VLSI development methodologies, design flows, and quality standards.
* Evaluate and select both digital and analog IPs required for the ASIC.
* Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.
Sub Department:
VLSI
City:
Rosh HaAyin.

We are seeking an experienced Infrastructure Engineer. with strong Linux knowledge to join our team. The ideal candidate will be responsible for planning, implementing, and maintaining our IT infrastructure, with a focus on high-performance computing environments for VLSI workloads. Primary responsibilities will include managing and maintaining HPC infrastructure and Storage in Linux-based environments for new and existing customers. Support operational and reliability aspects of large-scale clusters with focus on performance at scale, real time monitoring, logging, and alerting. Engage in and improve the whole lifecycle of servicesfrom inception and design through deployment, operation, and refinement.
Key Responsibilities:
Collaborating with FrontEnd, BackEnd, and Analog ASIC designers to develop and automate efficient, robust, and high-quality ASIC workflows and processes
Design, implement, and maintain on-premises and cloud-based IT infrastructure
Set up and manage Linux-based high-performance computing (HPC) clusters
Configure and optimize storage solutions (e.g., NFS, EMC Isilon, NetApp)
Implement and manage networking solutions, including 10/40 GB networks
Set up and maintain job distribution systems (e.g., Altair Accelerator)
Implement virtualization solutions (e.g., VMware)
Manage and optimize server deployments (e.g., HPE, Dell)
Implement and maintain data security strategies across multiple layers
Collaborate with cross-functional teams to ensure infrastructure meets the needs of R&D, Production, and other departments
Provide technical support and troubleshooting for infrastructure-related issues

We are seeking a highly skilled Program Manager to lead multi-disciplinary R&D projects encompassing ASIC (Application-Specific Integrated Circuit) design, hardware (HW) development, and software (SW) development.
The ideal candidate will have a strong background in program managing complex ASIC projects and a proven track record of successfully delivering projects on time and within budget. The role involves close Collaborate with cross-functional teams, including ASIC Group, Hardware Group, Software Group, and other stakeholders, to drive innovation and deliver cutting-edge solutions for space applications.
A key part of your role is working closely with customers to understand their needs, translate requirements into actionable plans, and ensure successful delivery of solutions that meet their expectations. You will be the primary point of contact, managing stakeholder communications.

we relentlessly strive to create products that enrich peoples lives. Are you passionate about solving unresolved challenges and revolutionizing the industry? We have an exceptional opportunity for an exceptionally talented IP timing lead to join our dynamic group. As a key member of this team, you will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers daily. This role is for an IP timing Engineer who will empower us to produce fully functional first silicon IP designs. Your responsibilities will encompass all phases of pre-silicon development, from defining the constraints to achieving high-quality tape-out..
Description
In this role, you will be responsible for developing and owning IP level Netlist generation (Synthesis, UPF , scan insertion, external IPs integration) & timing constraints, for both regular and custom requirements, from synthesis to sign-off, ensuring sign-off quality timing convergence. You will collaborate closely with the RTL designer to comprehend the design intent and clock structure, with the CAD team to understand and develop the flow, and with the Physical Design team to finalize and sign-off the timing. Additionally, you will actively contribute by generating ideas and plans to verify your own timing constraints. You will demonstrate innovation in timing constraints and flow to facilitate timing closure and address any potential pessimism or fallouts in timing analysis.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.

As part of our team, youll contribute to the development of our next-generation network devicesSilicon One. Our team operates in a startup-like environment within a stable and leading corporation.

What You'll Do:
You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are looking for a highly experienced and motivated VLSI Manager to lead the development of our next-generation ASICfrom initial concept to final production. In this pivotal role, you'll manage the entire ASIC development lifecycle, working closely with cross-functional teams and external partners to deliver cutting-edge technology that powers the future of autonomous vehicles.
Responsibilities
Own and lead the end-to-end ASIC development process.
Act as the central point of contact for all ASIC-related activities, collaborating with Product, Firmware, Computer Vision, Hardware, and other stakeholders.
Drive the ASIC program work plan, ensuring alignment and coordination across global teams and multiple workstreams.
Define and enforce VLSI development methodologies, design flows, and quality standards.
Evaluate and select both digital and analog IPs required for the ASIC.
Manage relationships and deliverables with external VLSI partners and service providers, ensuring high-quality outcomes.

we are looking for a Junior Design Engineer, Google Cloud, Network
Responsibilities
Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and field-programmable gate array/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

we are looking for a Design Verification Engineer, CPU, Google Cloud
As a CPU Design Verification Engineer, you will work as part of a Research and Development team, and you will build verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers in projects and perform direct verification. You'll build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full lifecycle of verification which can range from verification planning, test execution or collecting, and closing coverage.

Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog/UVM, or Specman.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Lead coverage measures to identify verification holes and to show progress towards tape-out.

As an Executive CPU Design Verification Engineer, you will be a part of Research and Development team to verify digital designs, develop constrained-randomn test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through rigorous corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/UVM or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.