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We are looking for a talented communication PHY algorithms engineer to join our growing, highly motivated, and skilled modem research team, to lead and participate in research of proprietary wireless communication signals and design modulators,
demodulators as part of our counter-drone cyber-based product.

Responsibilities:
Research and analysis of proprietary air interface: algorithm research of sampled wireless signals using MATLAB or Python, to define all radio characteristics including sample rate, modulation scheme, error corrections, spreading techniques and more.
Full modem implementation and simulation in MATLAB or Python.
Guide and support the FW, DSP and FPGA teams for concept implementation and debug.
Analysis and debug of PHY algorithms behavior and performance improvements.

AWS Utility Computing (UC) provides product innovations from foundational services such as Simple Storage Service (S3) and Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Annapurna Labs, as part of Web Services (AWS), is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

If you want to be part of a team that's advancing cloud computing technology at scale, join our Power Analysis, Optimization, and Management team, where you'll help develop advanced processors that power Cloud. We're looking for someone who combines strong technical knowledge in chip design with excellent problem-solving abilities and collaborative skills.

Key job responsibilities
- Analyze SoC Power consumption at Pre and Post Si stages
- Contribute to SoC Power optimization during all stages of Design Cycle
- Work with variety of teams to impact the quality of SoC power efficiency: Logic & Physical Design, PDN, Post-Si.
- Optimize Power Team analysis processes to raise effectiveness of our work.
- Solve challenging problems at daily basis.

A day in the life
- Work on state-of-the-art processor technology
- Engage in the complete chip development cycle, from initial architecture through post-silicon analysis
- Solve complex, multidisciplinary challenges
- Collaborate with talented teams across the organization
- Contribute directly to next-generation cloud computing solutions

About the team
Annapurna Labs started in 2011, as a fabless chip start-up, focused on bringing innovation to the fast-growing cloud infrastructure. Four years after its inception, Annapurna Labs was acquired by Web Services (AWS). Since then, we have accelerated innovation and developed a number of products that benefit cloud customers, including AWS Nitro technology, AWS Graviton processors, AWS ML Inferentia & Trainium and more. Although Annapurna Labs is a small company, it is significant for AWS, with a reputation of being the key ingredient in the "secret sauce" behind its success. The Annapurna Labs team is responsible for building custom chips, accelerators, and software stacks that run on top of them, which gives us the possibility to optimize and improve our products in different layers more effectively.

Diverse Experiences
values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage you to apply. If your career is just starting, hasnt followed a traditional path, or includes alternative experiences, dont let it stop you from applying.
Why AWS
Web Services (AWS) is the worlds most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and have never stopped innovating. Thats why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Work/Life Balance
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why flexible work hours and arrangements are part of our culture. When we feel supported in the workplace and at home, theres nothing we cant achieve in the cloud.
Inclusive Team

well give you the opportunity to harness all thats within you by working in teams of diverse and high-performing employees, tackling some of the most important health industry challenges. With access to the latest tools, information and training, well help you in advancing your skills and career. Here, youll be supported in progressing whatever your ambitions.

About the role:
a worldwide and diverse company who puts patients first. Through this position, the ideal candidate would use their systems engineering and risk management experience to support, develop, establish and maintain Medical Electrical Equipment/Systems (MEE / MES) and associated accessories for New Product Development (NPD) Engineering within the Urology Division of (BSC).
Our team is all about building the future of the operating room for Urologists.

As the industry leader in surgical kidney stone treatment, we are on a mission to empower physicians to treat more cases, more efficiently, with better outcomes; To help patients in need get back to their daily lives. As a Principal Design Quality Assurance (DQA) Engineer, youll be at the heart of that mission to develop and support best-in-class products to bring advanced, safe innovations to the clinic. You will also be leading the effort to develop MEE / MES. Your contributions will directly impact patient care at a company widely regarded as being a quality leader in the medical device industry.

Your responsibilities include:
Lead product teams within the BSC Quality System to develop new MEE and MES as part of a core group of DQA Engineers supporting the Laser Therapies franchise. Special focus on:
Engagement with project teams for Systems Engineering and Systems Risk Management as a Subject Matter Expert (SME).
Utilize Systems Engineering practices to lead efforts for requirements management/system architecture to align risk mitigations with design inputs, design outputs at different levels (e.g., system / sub-system) for products that are both stand alone, and network connected.
Lead NPD projects as a DQA SME and work with R&D Product Development Engineers to review Hardware/Software systems architecture(s) and identify possible failure modes/risk control opportunities for these complex systems.
Lead Risk Management activities during all phases of Electrical HW/SW design, using design quality assurance principles applicable to FDA/EUMDR-Regulated Class II Medical Device environments (including interconnected software systems).
Participate and lead in the creation and maintenance of Risk Management and Usability deliverables.
Lead and/or support development of NPD Reliability Engineering Program Plans and related reliability program activities.
May perform other duties as directed.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Workload Analysis Researcher within our company Cloud's MSCA organization, you will be integral to developing silicon solutions powering our company's direct-to-consumer products. You will join a Research and Development team focused on analyzing and profiling workloads requirements within the company Cloud environment. Your role will involve conducting in-depth research on CPU optimization, feature development, and ML usages over compute platforms, contributing to identifying key areas of investment and future opportunities. This role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. Your work will directly influence the next generation of hardware experiences for millions of our company users and Cloud customers.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are company , Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Plan and execute detailed analysis of CPU workloads within the company Cloud infrastructure, analyze trends and map future requirements.
Collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to CPU performance and efficiency.
Develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on our company Cloud platforms.
Analyze the impact of machine learning applications on CPU usage, identifying opportunities for optimization and feature enhancements.
Lead the investigation and development of metrics to measure CPU performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

Power the Future with us! At our company we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. The Integration Engineer will develop, perform and analyze system Validation tests and will take part in the system review processes, with an understanding of the market requirement, system design, and the end users expectations. What will you be doing?
* E2E responsibilities for SolarEdge system, and product validation and experiments.
* Plan and execute HW & SW system integration tests.
* Understand and study the system operation edges, and system design edges.
* Plan and design manual and script automation tests of our Product
Country:
Israel
City:
Herzliya

We are looking for some exceptional talent to join our System Integration Engineering team as a System Integration Technician.

Your Day to Day
Design and develop integrations at the system-level, encompassing both hardware and software, among multiple system components.
Collaborate with cross-functional teams (architecture, hardware, software, Algo, QA, Electro-Optics, photonics etc..) to gather integration requirements. Plan and execute the system integration accordingly.
Troubleshoot and debug integration issues.
Develop, execute, and document integration tests to ensure both the quality and completeness of the integration process.
Construct, maintain, and improve systems in the prototype phase or during proof-of-concept, as part of the teams effort to introduce new sensing capabilities to our product.
Plan and execute data collection tests, then analyze the results to provide insights that enable development teams to improve the system.

You'll be joining our Physical Design team which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Static Timing Analysis, Design Floor Planning, Physical Verification.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Join the team and be part of the cutting-edge innovation that drives our next-generation network devices.
Our unique team operates in a startup-like atmosphere within a stable and leading corporation, working on some of the most advanced silicon technologies. Our design center is home to all silicon hardware and software development disciplines, creating an environment that fosters collaboration and technical excellence.
We are redefining the industry and building the next-generation internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation for all of future routing products. we deliver high-speed networking while ensuring programmability, power efficiency, and scalability across a range of service provider and web-scale markets.
Your Impact:
As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.