לוח משרות דרושים

The Global Product Training team is looking for a Technical Trainer to join our training team, lead product line training activities and take full ownership of training processes across the product lifecycle. This role combines hands-on training delivery with content development, working closely with multiple interfaces across the organization.
What will you be doing:
Act as a one-stop shop for product training activities from A to Z throughout the product lifecycle
Deliver training programs to global audiences, including classroom sessions, on-tool training, remote sessions, and webinars for both internal teams and customers worldwide
Lead structured training courses.
Develop and maintain training materials for new and existing products, including building syllabi, creating presentations, and editing training videos
Continuously update and improve training content based on product updates and field feedback
Work closely with R&D, Service, and System teams to gather knowledge, translate technical information into training content, and ensure alignment with production and field requirements
Balance between delivering training sessions and developing high-quality learning content

We are seeking PHY Algorithm Engineer, Silicon One Israel
Meet the Team:
You will join the SerDes System Algorithm team within Silicon One in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
We are at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact:
As a PHY Algorithm Engineer, you will develop, model, configure, and optimize algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, using MATLAB for algorithm development from the idea to advanced SerDes systems.
Research, design and develop PHY and modem algorithms for high-speed SerDes devices.
Build and use system models to analyze modem behavior, signal-processing performance, and algorithm tradeoffs.
Configure, tune, and optimize modem behavior to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Collaborate with silicon hardware and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

We are seeking a skilled and experienced Software Engineer to develop a Go-based control plane within Kubernetes, with a focus on traffic security. You will be responsible for building and enhancing a Kubernetes-native control plane to provide seamless management of our eBPF datapath, enabling a secure traffic management in cloud and hybrid enterprise environments. You will work with a highly collaborative and skilled team to build solutions that advance the next generation of networking and security in Kubernetes environments.
Design and develop a Go-based control plane managing our enterprise-grade traffic security engine.
Develop APIs, tools, and custom resources to streamline secure traffic management, scaling, and failover within Kubernetes environments.
Debug, troubleshoot, and resolve performance, reliability, and security issues in the control and dataplane.
Participate in code reviews, architectural discussions, and contribute to technical documentation.

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.