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A leading supplier of custom SOC and security hardware solutions for the computing and server markets. As a well-established and independent design center, we collaborate closely with top-tier customers such as HP, Dell, Qualcomm, Microsoft, and Google to develop advanced solutions that secure, control, and manage our customers platforms. We are seeking a talented and experienced Chip Architect to join our team. The ideal candidate is a self-motivated, fast learner with a strong background in hardware and system architecture. This role requires a technology leader capable of driving multidisciplinary programs and working closely with customers and internal teams across the entire product lifecycle.
Responsibilities:
* Translate customer and marketing requirements into detailed SOC architectural specifications
* Provide functional specifications for chip hardware design and Embedded software development
* Lead architectural decisions and serve as a technical authority across cross-functional teams
* Collaborate with customers and marketing to refine product requirements and align on technical solutions
* Support design, implementation, and verification processes throughout development
* Participate in system debugging, root-cause analysis, and issue resolution
* Support post-silicon bring-up, system integration, and software enablement

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.

we're seeking a visionary ASIC Design Student to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, designing complex solutions that sit at the heart of our most ambitious connectivity projects.

As an ASIC Design Student, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving unnamed challenges in deep-submicron processes and want to shape the digital design foundation for AI infrastructure connectivity, this is your opportunity.



Key Responsibilities

Assist in the development of micro-architecture, RTL coding, and debugging for complex digital blocks
Utilize industry-leading EDA tools (Lint, CDC, Synthesis) to ensure designs are robust and power-efficient
Work closely with the verification team to run simulations, analyze results, and ensure design quality
Interact with Architecture and Backend teams to understand the full chip development lifecycle
Help leverage AI-based automation tools to optimize engineering workflows

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews

we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities


Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

We are seeking a HW Board Design Engineer.
Meet the Team
Youll collaborate with top industry engineers within the fast-growing Silicon One group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices-Silicon One. Our team operates in a startup-like atmosphere within a global, leading corporation.
Our design center is unique, hosting all silicon hardware and software development fields under one roof. Our Networking Chips deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. They are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Your Impact
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.
Define product specifications, develop electrical schematics, and guide component selection.
Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.

We are seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

Key job responsibilities
Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation - spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.

Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.

Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.

Engage with leadership: Communicate strategy, progress, and risk to senior leadership. Influence the overall silicon roadmap with analog capabilities and constraints.

We are seeking for an board design. A leading technology company is looking for an electronics engineer to design and edit electronic cards (board design), from the initial development stage to transfer to production and support throughout its entire life cycle. The role combines work on a wide variety of projects and technologies, in a dynamic environment that requires mental flexibility and the ability to work on several advanced tasks.
Responsibilities
Design and edit printed circuit boards (PCB) from the schematic to layout stage. Development of electronic boards combining: microcontrollers, digital and analog systems, sensors, communication interfaces, power supplies (power), etc. Support cards from the initial development stage to the final product. Work with production - transfer cards to production, testing and production of revisions. Perform several revisions to cards at levels Various designs. Work on multiple projects at a time and at a fast pace of development.
Location: Rishon LeZion, full-time, Sunday-Thursday

Required IC Package Layout Designer
Job Description
Meet the Team
Join the Package Design Team at Silicon One in Israel, a group leading the way in developing our groundbreaking silicon solutions for next-generation networking. As a collaborative team at the center of our silicon development, we design and optimize advanced package solutions for some of the industrys most sophisticated ASICs. Youll work directly with experts in layout, signal integrity, and power distribution, shaping innovative methodologies and driving the evolution of high-performance networking technologies.
Your Impact
This role offers a unique opportunity to make a significant impact on the future of networking innovation within the Silicon One initiative. As a layout engineer, you will drive the entire package design layout process-from planning and optimization to execution-ensuring the delivery of high-speed, robust, and scalable solutions for global networks. You will work closely with engineers, define strategies, and collaborate across multi-functional teams to accelerate the creation of industry-leading packages. Youll join a passionate community dedicated to changing how the world connects, works, and learns, while building strong partnerships and fostering collective success.
Responsibilities:
Lead package layout design while planning and driving schedules from initial concept through full implementation.
Optimize package pinouts, stack-ups, power distribution, and high-speed routing, balancing performance and manufacturability
Collaborate with signal integrity (SI) and power integrity (PI) teams to ensure design quality and efficiency
Enhance design methodologies and partner with vendors to improve product quality and efficiency
Drive innovation in package solutions for our next-generation ASICs.

We are seeking a HW Board Design Engineer.
Meet the Team
Youll collaborate with top industry engineers within the fast-growing Silicon One group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices-Silicon One. Our team operates in a startup-like atmosphere within a stable and leading corporation.
Our design center is unique, hosting all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry and building a new internet for the 5G era, with a unified, programmable silicon architecture that will be the foundation of all our future routing products.
Our devices are designed to be adaptable across service providers and web-scale markets, crafted for both fixed and modular platforms. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. Silicon One is a transformative technology set to serve our customers and end-users for decades to come.
Your Impact
Spearhead innovative switch system design, guiding the process from concept through to mass production.
Collaborate with cross-functional teams in areas such as board design, mechanics, thermal, PCB layout, production, software/firmware, RTL, and more.
Act as the technical focal point and decision-maker for the project.
Conduct hands-on testing in a lab environment and support production and qualification stages.
Define product specifications, develop electrical schematics, and guide component selection and layout processes.

we are looking for a Senior Board Design Engineer.
As a Hardware Board Design Engineer , you will own the electrical design of complex Big Data Analytics systems. You will drive the development of next-generation Analytics Processing Unit (APU) accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. You will work cross-functionally with Silicon (ASIC), Signal Integrity, Power, Mechanical, and Manufacturing teams to bring products from concept to mass production.
Responsibilities:
Lead the schematic capture and component selection for high-density, multi-layer Printed Circuit Boards (20+ layers) incorporating high-power ASICs (APUs) and high-speed memory (LPDDR5/DDR5).
Design and validate high-speed interfaces including Peripheral Component Interconnect Express (PCIe) Gen 5, DDR5 and LPDDR5.
Collaborate and manage Signal Integrity (SI) engineers to define routing constraints and stack-up.
Work closely with PCB layout designers to guide placement and routing of critical signals and power planes.
Lead the lab bring-up of first silicon/first board. Debug complex hardware issues. Root-cause failures to component, assembly, or design issues

we are a global leader in the development and manufacturing of advanced infrared detectors and electro-optical solutions for defense and commercial applications.
We are seeking a skilled board designer with extensive experience in high-speed digital design to join our Board Design R&D Team. In this role, you will define system and hardware requirements, design FPGA-based hardware platforms, and validate high-speed interfaces such as DDR4, USB3, Ethernet, MIPI, and Camera Link. You will work closely with firmware, software, and mechanical engineers to deliver robust, production-ready Embedded systems for advanced electro-optical products.
Key Responsibilities
Define hardware requirements and prepare detailed design documentation for FPGA-based boards, including power architecture, configuration, and peripheral circuitry.
Develop schematics and oversee PCB layout for complex, high-speed multilayer boards.
Perform hardware simulations and signal analysis using tools such as LTspice and Cadence.
Design and validate high-speed interfaces including DDR4, USB3, Ethernet, MIPI, and Camera Link.
Define and manage PCB stack-ups, impedance control, differential pair routing, and high-speed layout constraints.
Conduct Signal Integrity (SI) and Power Integrity (PI) analysis to ensure performance, robustness, and reliability.
Lead prototype bring-up, testing, and debugging using lab equipment (oscilloscopes, logic analyzers, VNAs).
Collaborate with firmware, software, and mechanical teams to ensure full system integration.
Participate in design reviews, DFM/DFT processes, and continuous design improvements.
Support production and NPI activities, and resolve hardware-related manufacturing issues.