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24/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities
Execute SoC Top-level physical design and actively drive full-chip convergence.
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff.
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR).
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon.
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration.
Requirements:
Basic Qualifications
B.Sc. or M.Sc. in Electrical Engineering.
5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies, working on advanced process technologies (5nm, 3nm, and below).
Proven experience executing complex block or chip-level projects with a proactive, "can-do" approach and excellent communication skills.
Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR.
Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus).
Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration.


Preferred Qualifications
Deep understanding of Power & Noise analysis (EM/IR).
Experience with DFT (Design for Test) integration into the physical design flow.
Background in high-speed interfaces or data center protocols.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/10/2026
Location: Herzliya
Job Type: Full Time
Nuvoton Israel is a leading supplier of custom SoC and security hardware solutions for the computing and server markets. As a well-established and independent design center, we collaborate closely with top-tier customers such as HP, Dell, Qualcomm, Microsoft, and Google to develop advanced solutions that secure, control, and manage our customers platforms. We are seeking a talented and experienced Chip Architect to join our team. The ideal candidate is a self-motivated, fast learner with a strong background in hardware and system architecture. This role requires a technology leader capable of driving multidisciplinary programs and working closely with customers and internal teams across the entire product lifecycle. Responsibilities:
* Translate customer and marketing requirements into detailed SoC architectural specifications
* Provide functional specifications for chip hardware design and embedded software development
* Lead architectural decisions and serve as a technical authority across cross-functional teams
* Collaborate with customers and marketing to refine product requirements and align on technical solutions
* Support design, implementation, and verification processes throughout development
* Participate in system debugging, root-cause analysis, and issue resolution
* Support post-silicon bring-up, system integration, and software enablement
Requirements:
* BSc or MSc degree in electrical / computer engineering
* 5+ years of proven experience in SoC/board design and architecture (mandatory)
* Strong VLSI/board design background (mandatory)
* Board and system design understanding
* Excellent analytical, communication, and leadership skills
* Ability to work effectively in a cross-functional, multidisciplinary environment
* Highly motivated with strong self-learning capabilities Advantages:
* Experience with standard interfaces (e.g., USB, SPI, I2C, etc.) - Advantage
* Experience in board/system design and integration - Advantage
* Experience in embedded software - Advantage
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Requied Full Chip CAD Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Develop script in Synopsys TCL and Python.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in electronic design automation (EDA) tools and RTL2GDS flows.
Experience in the semiconductor/EDA industry.
Preferred qualifications:
Masters degree in Computer Engineering/Electronics Engineering, or a related field.
Experience with silicon quality or reliability.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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28/09/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Perform physical layout for full-chip level, integration, pinning and bump route.

Work with block owners and project managers to assure high quality convergence in all layout aspects.

You will be responsible for chip layout from the floorplanning stage through tape-out.
Requirements:
What we need to see:

An Electronics Engineer certificate or a B.Sc. in Electrical Engineering.

You should have 5 years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodologies, including DRC, LVS, ANT, ERC, and DFM for advanced process nodes, is required.

Knowledge in scripts' language: TCL, Unix and Shell.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre).

Self-motivation, attention to detail and good interpersonal skills.


Ways to stand out from the crowd:

Experience in methodology definition / flow owner of Full-chip / Place and Route.

Great teammate.

Ownership, self-learning skills and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8836166
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Physical Design Lead, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, youll work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
Youll be part of a team that pushes boundaries, developing, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You'll contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Responsibilities
Lead physical design of complex SoC to tape-out while working with multiple team members.
Evaluate and develop physical design methodologies and decide on the SoC flow.
Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design tradeoffs for physical design closure.
articipate in design reviews and track issue resolution, and engage in technical and schedule tradeoff discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.
Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
Experience in silicon implementation and chip integration.
Experience in ASIC development teams.
Experience in managing physical design teams working on digital designs that produce and deliver silicon.
Preferred qualifications:
Experience in extraction of design parameters and analyzing data trends.
Experience and breadth in engineering across physical design, top-level implementation, GDS tape-out.
Experience in top-level floor planning, block integration, static timing analysis, and sign-off.
Understanding of circuit design, device physics, and deep sub-micron technology.
Knowledge of delivery of high complexity silicon in technology process nodes.
Ability to lead cross-functional teams.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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24/09/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling our products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities
Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing.
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration).
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices.
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints.
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance.
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets.
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp.
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews.
Requirements:
Basic Qualifications
10+ years of hands-on IC BIG package design experience for high-performance semiconductor products, with full ownership from concept through tape-out.
Expert proficiency in IC package design tools (Cadence APD / SiP or equivalent) and experience designing complex packages (BGA, FCBGA, FCCSP).
Strong package architecture & integration expertise, including stack-ups, ball/bump maps, constraints, SMT integration, and package BOM ownership.
Deep understanding of signal, power, and thermal integrity at the package level, with ability to drive design tradeoffs based on analysis.
Proven manufacturing and release experience, including DRC/LVS/DFM, OSAT engagement, and delivering production-ready package designs.

Preferred Qualifications
Experience with AI, networking, PCIe, CXL, or other high-speed data center interfaces.
Familiarity with package reliability standards and qualification (JEDEC, IPC, thermal cycling, HTOL, etc.).
Experience supporting chiplet-based architectures and heterogeneous integration.
Prior technical leadership or package ownership on high-volume products.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required SoC Chip Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Chip Architect, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for our Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.
You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Cloud and our flagship AI services.
Responsibilities
Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software.
Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC).
Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency.
Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads.
Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
15 years of experience leading the architectural definition of high-performance SoCs, ASICs, or multi-chiplet systems from concept through production.
Experience architecting SoC interconnects, memory hierarchies, and system-level fabrics.
Experience writing, owning and maintaining comprehensive SoC architecture specifications.
Experience working across hardware, firmware, and system software boundaries with system-level reasoning.
Preferred qualifications:
Masters degree or PhD in Electrical Engineering or Computer Engineering.
Experience with AI workload analysis, their mapping across different data center system components, and optimizing hardware solutions to better serve them.
Experience scaling and optimizing high-performance AI accelerators, compute chiplets, or IO Hub SoCs for data center/cloud deployments.
Proven track record of architecting multi-chiplet systems utilizing cutting-edge silicon process technology and advanced packaging (2.5D/3D, D2D interfaces such as UCIe, BoW, or high-speed SerDes).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Yokne'Am Illit
Job Type: Full Time
We are pioneering the future of medical diagnostics with our innovative capsule endoscopy solutions. Imagine a world where diagnosing gastrointestinal conditions is as simple as swallowing a pill which captures with imagers and different sensors the digestive system and transmit it in real time. Our cutting-edge technology not only makes this possible but also revolutionizes the patient experience, providing a non-invasive, accurate, and efficient diagnostic tool. We are seeking a dynamic and visionary Analog and RF engineer to join our dedicated team, driving the development and integration of our next-generation capsule endoscopy devices.
As a Senior Analog & RF Engineer specializing in capsule endoscopy development, you will play a key role in the design, development, and integration of the critical analog and RF communication path between the capsule, located inside the patients digestive system, and the external recorder worn by the patient.
You will be responsible for developing high-performance, low-power analog and RF solutions that enable reliable wireless communication, contributing directly to the performance and advancement of our next-generation medical devices.
In this critical role, you will collaborate closely with System Engineers, PCB design and Layout, Firmware Developers, Modem Algorithm Engineers, and Mechanical Design teams to develop and integrate advanced solutions across the system. You will work in a highly collaborative, open-minded environment that encourages new ideas, creativity, and innovation, contributing to cutting-edge medical technology that enhances patient care.
Primary responsibilities:
Own and drive the Analog & RF communication path from architecture definition through detailed design.
Work closely with leading semiconductor suppliers and technology partners on a system on Chip definition, development, and integration of custom IC/ASIC solutions, contributing to system architectural decisions and ensuring alignment with system-level requirements.
Research, evaluate, and define communication receiver and transmitter architectures, including Zero-IF, Low-IF/NZ-IF, Superheterodyne, and other relevant architectures, based on system requirements and product constraints.
Perform system-level RF and Analog analysis, including noise budget, link budget, dynamic range, sensitivity, linearity, distortion, interference, and overall communication-channel performance.
Develop simulation models and methodologies to evaluate communication-channel performance and validate architectural and design decisions prior to hardware implementation.
Design and specify the Analog transmitter and receiver signal paths, including filtering, amplification, gain stages, matching networks.
Analyse and optimize antenna design and RF performance, including antenna matching, efficiency, radiation characteristics, impedance, and interaction with the capsule and surrounding biological environment.
Drive a system on chip designs from proof-of-concept and laboratory prototypes into production-ready medical devices.
דרישות:
BSc \ MSc in Electrical Engineering.
7+ years of hands-on experience in very Low power Analog and RF engineering, preferably in wireless communication systems, RFICs, or mixed-signal systems; Familiarity with SoC/mixed-signal architecture, including considerations for integrating analog, RF, digital, and power-management functions.
Strong understanding of RF and analog communication architectures, including Zero-IF, Low-IF/NZ-IF, Superheterodyne, and related receiver/transmitter architectures; Proven experience with analog/RF transmitter and receiver design, including filters, amplifiers, LNAs, PAs, mixers, matching networks, and signal-conditioning circuits; Strong understanding of PCB-level RF implementation, including layout, grounding, shielding, power integrity, signal integrity, and RF isolation.
Preferred Qualifications:
Experience in writing design and technical specifications.#EN המשרה מיועדת לנשים ולגברים כאחד.
 
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27/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.

As a SIP team member, you will assume responsibility for all electrical aspects of physical interfaces of advanced I/Os, PLL, Memory and SerDes interfaces, from integration at the Die level, through SI/PI simulation and package layout, to reference board design aspects.

This position is for an experienced engineer with strong background in high-speed electrical interfaces, such as DRAM, PCIe, Ethernet SerDeses. The line of work is multi-disciplinary, combining Package-Design, Back-End integration of electrical IPs, SI/PI extractions & simulations.


Key job responsibilities
Deep dive into electrical IPs, integrated into the DIE;
I/O ring design and close work with Backend team on floor-planning all I/O interfaces at the DIE level.
Lead test studies of Die bump-out arrangements and Package substrate breakout.
Lead layout test studies of package pin-out arrangements and PCB board breakout.
Design large and complex package substrates.
Carry advanced SI/PI extractions and simulations to validate the design from the silicon to the peer device at the board level.
Requirements:
Basic Qualifications
- BSc or MSc in Electrical Engineering or in related field.
- At least 8 years of experience in a similar role.
- Experience in Layout (PCB or Package), or BackEnd integration of electrical IPs.
- Familiarity with Signal and Power integrity simulation tools.

Preferred Qualifications
- Knowledge of Chip, Package and PCB co-design methodology.
- Knowledge in high-speed digital interfaces such as DRAM/PCIe/SerDes.
- Knowledge in power-integrity and power-delivery of low-voltage high-current
- Hands on experience with lab testing and characterization.
- Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice).
This position is open to all candidates.
 
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27/09/2026
Location: Haifa
Job Type: Full Time
We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.
Requirements:
Basic Qualifications
- BSc in Electrical Engineering or in related field.
- Background in board design, or lab measurement of digital high-speed interfaces.
- Familiarity with Signal and Power integrity simulation tools.

Preferred Qualifications
- Familiarity with high-speed digital interfaces such as DRAM/PCIe/SerDes.
- Previous experience with lab equipment (e.g oscilloscope, spectrum analyzer).
- Familiarity with simulation/extraction tools (e.g. HFSS, Sigrity, HSpice).
This position is open to all candidates.
 
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24/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks.
Develop and maintain System Verilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing.
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified.

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process.
Drive designs toward 100% verification closure through comprehensive test development.
Contribute to verification methodology improvements and best practices.

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle.
Apply analytical skills and debugging techniques to solve intricate verification challenges.
Collaborate effectively in a fast-paced, team-oriented R&D environment.
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering or related technical field.
3+ years of proven experience in ASIC verification within the semiconductor industry.
Hands-on experience developing components within complex verification environments using System Verilog.
Strong working knowledge of standard verification methodologies, specifically UVM.
Sharp analytical mind with passion for debugging and technical problem-solving.
Excellent communication skills with ability to thrive in collaborative R&D environments.

Preferred Qualifications
Master's degree in Electrical Engineering or related field.
Familiarity with Formal Verification or Emulation flows.
Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks.
Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL.
Experience with assertion-based verification and constrained-random testing.
Background in connectivity or networking silicon verification.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8831988
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Location: Herzliya and Haifa
Job Type: Full Time
As an ASIC Design Engineer in the IP design team, you will work closely with architecture, design, and verification teams to build high-performance designs. Apply your knowledge of computer architecture and digital design to enable high-bandwidth processing pipelines!
Responsibilities
Coding high-quality RTL, with embedded assertions and cover points
Writing detailed micro-architectural specifications
Collaborating with multi-functional teams to explore solutions that improve performance while minimizing power and area
Working closely with design verification and formal verification teams to debug and verify functionality and performance
Requirements:
Minimum Qualifications
5+ years of experience in digital design
Prefer previous experience in USB4, USB3, PCIe, and/or DisplayPort
Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug
Good collaboration skills with strong written and verbal communication skills
Familiarity with low-power design techniques such as clock- and power-gating is a plus
Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks
Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with AI/ML applications, relevant scripting languages (Python, Perl, TCL)
Preferred Qualifications
BS.c / MS.c in EE/ CE
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8865376
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Engineer, Cloud, Networking
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead an ASIC subsystem and understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Experience in TCP, IP, Ethernet, PCIe, DRAM, Network on Chip (NoC) principles and protocols.
Experience in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8843822
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05/10/2026
Location: Ahihud and Karmiel
Job Type: Full Time
Semi Conductor Devices (SCD), a leading worldwide supplier of high-end Infrared Detectors and thermal imaging cores, is looking for an Analog / Mixed-Signal VLSI Designer to join its VLSI R&D group. The role involves design and validation of custom analog and mixed-signal ASICs (ROICs) for advanced IR imaging systems, working closely with experienced analog, digital, system, and hardware teams.
Responsibilities:
Design and verify Analog and Mixed-Signal circuit blocks for IR image sensors (ROICs) under the guidance of senior designers Participate in the full ASIC development flow: specification review circuit design verification integration silicon bring-up lab validation Contribute to block-level simulations, documentation, and design reviews Work closely with digital designers, layout engineers, electronics, and system teams to support chip integration Support post-silicon validation and lab measurements, including debug and correlation to simulations Gain exposure to advanced CMOS processes, image sensor architectures, and system -driven design constraints.
Requirements:
Basic requirements BSc / MSc in Electrical Engineering.
2-5 years of hands-on experience in analog or mixed-signal VLSI design (industry or advanced academic work).
Basic understanding of analog design fundamentals: gain, bandwidth, noise, stability, matching, PVT effects.
Experience reading and working from specification documents.
Familiarity with analog simulation and schematic tools (e.g., Cadence Virtuoso / ADE / Spectre).
Ability to work well in a team-oriented, multidisciplinary environment Good written and spoken English.
Advantages:
Experience with image sensors, ROICs, or custom mixed-signal ASICs. Design experience with one or more of the following:
o Analog front-ends, amplifiers, bias circuits.
o ADCs or data converters o Low-noise and/or low-power analog design. Exposure to silicon bring-up and lab validation.
Strong motivation to learn, take responsibility, and grow as an analog designer.
Location: Near Karmiel.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8793574
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Location: Hod Hasharon and Haifa
Job Type: Full Time
Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.
Requirements:
BSC, MS or PHD in Electrical Engineering, Computer Engineering, or Computer Science.
Good understanding of general purpose CPU micro-architecture, including knowledge of areas such as processor pipelines, load store units, caches, cache coherence, memory hierarchy, multi-processor, multi-thread processor systems, memory controller.
Good understanding of high speed digital VLSI design flow and methodology
Understanding of trade-offs between power, performance and area appropriately to meet the requirements of the product.
At least 6 years of experience in one of the leading CPU companies
Familiarity with the ARM\IA architecture and the micro-architecture for current ARM\IA CPU cores.
Software development (C, assembly).
Hands on experience as a Front end ASIC designer
DESIRED
Co-operate and communicate well with the architecture team and other members of the development.
Excellent verbal and written communication skills.
Travel to Beijing and ShenZhen sites may be required.
Good presentation and internal customer interaction skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8842804
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