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We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.

We are seeking an exceptional architect to join our architecture team and shape the future of quantum control. We have a unique opportunity to shape the architecture of next-generation quantum computers toward utility-scale quantum computing.
In this role, you will define the logic architecture of the devices that are the heart of the next-generation quantum control platform. Designing the devices, including the pulse processor and their interfaces, requires a deep understanding of quantum computing, the system tradeoffs, and product requirements.
In this role, youll collaborate with Product and with the other members of the architecture team to define the requirements and the roles and responsibilities of each component. Youll identify system-level tradeoffs and identify solution alternatives. Youll work closely with the logic design and compiler teams to define a winning architecture.
Responsibilities: 
Architecture for the next-generation quantum control platform devices, ASIC, and logic components.
Define system-level architecture and features, providing detailed specifications to the various R&D teams.
Collaborate with the product and research teams to transform high-level requirements into architecture and spec definitions, and present tradeoffs.
Work with partners and vendors on requirements, integration architecture and joint development to optimize the product capabilities.

we are looking for a Senior HW architect
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

we are looking for a AI architect/ microarchitecture.
Job Description:
Define the AI core architecture that will shape the next generation of AI chips, leading the global competition in AI computing power. As a key contributor to the competitiveness of AI core architecture, we drive chip architecture innovation starting from algorithm evolution, building a full-stack closed-loop capability of "algorithm-architecture-circuit-system," and creating a globally leading, independently controllable AI accelerator core to support the Ascend AI ecosystem and the implementation of large model strategies.
Responsibilities:
Lead next generation inference solution optimized for power, performance and area. Considering scalable solution for large scale systems with many resources. Covering efficient data delivery and workload map.

We are looking for a phenomenal Ethernet HW Simulation developer for the ChipSim Group. You will join the ChipSim growing team and take our product to next level, working closely with HW design and architect teams and gaining a deep understanding of our products and technologies.
What Youll Be Doing:
You will be responsible for learning, developing, and delivering new Networking features in simulation.
Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex physical-layer behaviors in software.
Extend and optimize the simulation infrastructure by contributing to CI pipelines, automated test frameworks, and regression tools.
Support internal users by debugging simulation flows and collaborating on bug resolution.
Take part in future-facing innovation by enabling simulation for next-generation devices and features.

Required SoC Security Architect, Cloud Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an Edge-Artificial Intelligence product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical. You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge.
As a Silicon Security Architect, you will be responsible for the "Security-First" mindset of our custom silicon. You will define the hardware security primitives that protect our infrastructure from the foundation up. You will bridge the gap between traditional architectural security (like access control and cryptography) and the physical reality of silicon (protecting against sophisticated lab-based attacks). You will define methods to protect sensitive information by silicon countermeasures. You will ensure that our accelerators are not only performant but also impenetrable to a wide range of adversaries.
Responsibilities
Define and document the security architecture and flows for systems on a chip (SoCs), covering hardware root of trust, secure boot, and cryptographic acceleration.
Lead the strategy and implementation of countermeasures against physical attacks, including side-channel analysis, fault injection, and silicon invasive attacks.
Conduct threat modeling and risk assessments for SoC subsystems, balancing security with power, performance, and area constraints.
Collaborate with hardware design and verification teams to ensure security features are implemented and resilient against both logical and physical vectors.
Drive the evaluation and selection of security intellectual property (IP), and provide technical leadership during multi-functional design reviews.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs.
This simulation platform enables our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.
What Youll Be Doing:
Develop and maintain simulation components for the physical layer of our high-performance networking chips (e.g., GPUs, switches, NVLink, Ethernet...).
Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex physical-layer behaviors in software.
Define, implement, and validate simulations of features such as link training, error injection, and transceiver behavior, making the simulation platform a go-to internal platform for development and debugging.
Extend and optimize the simulation infrastructure by contributing to CI pipelines, automated test frameworks, and regression tools.
Support internal users by debugging simulation flows and collaborating on bug resolution.
Take part in future-facing innovation by enabling simulation for next-generation devices and features.

As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

We are looking for a phenomenal engineer to join the chip simulation team for networking chips and GPUs. This simulation platform enables Our engineers across firmware, SDK, and OS domains to develop and test their code without relying on physical hardware. If you're a creative, self-driven engineer passionate about systems-level design and eager to build technology that empowers internal teams, we want to hear from you.
What Youll Be Doing:
Develop and maintain simulation infrastructure components for different simulation teams (GPUs, switches, NVLink, Ethernet, PHY) of our high-performance networking chips.
Define, implement, and validate simulations of core infra features, improve performance, maintain multi processes and multi-threaded IPC mechanisms (sockets, queues etc.), define architecture and the building blocks of the simulation.
Own, extend and optimize all the CI/CD of the simulation team, starting from servers installation to adding and maintaining various Jenkins jobs that help developer and improve their life.
Collaborate with chip architects, firmware developers, and hardware design teams to accurately simulate complex behaviour in software.
Support internal users by debugging simulation flows and collaborating on bug resolution.
Take part in future-facing innovation by enabling simulation for next-generation devices and features.

We are seeking a driven and technically exceptional Firmware Manager to lead pre-silicon firmware development within the NVLink Switches & GPU Networking group In Tel-Aviv/Raanana.
This is a unique opportunity to be at the very front of networking innovation - shaping the firmware that powers our next-generation NVLink interconnect technologies before silicon even exists.
You will be responsible for the pre-silicon execution and strategy end-to-end: from early initiation and architecture engagement, simulation environments to model-based development and hardware-based bring-up. You will operate across multiple fields influencing outcomes beyond your direct team through strong technical authority and multi-functional cooperative efforts. The work environment is dynamic, exciting, and fast-paced. Are you ready for the challenge?
What you will be doing:
Lead, mentor, and grow a team of highly skilled firmware engineers, fostering a culture of ownership and innovation.
Drive the development planning and execution for the FW for NVLink Switch - from architecture definition through emulation validation and simulation platforms.
Navigate firmware development across all layers: low-level silicon bring-up, SDK interfaces, HW and OS integration.
Proactively identify development risks and drive mitigation plans through to resolution, owning program planning and schedule, from pre-silicon to post-silicon.
Continuously evolve pre-silicon development processes, toolchains, and methodologies and innovate to increase team velocity and first-silicon success rates.
Innovate! Bring our Networking products to shine in customers view.

we are seeking a Lead System Architect to join our system architecture team and help define the next generation of our AI-SuperNIC scale-out chip.
AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.
You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.
Responsibilities:
Define product requirements and architecture for next-generation ultra low-latency AI-SuperNIC
Design end-to-end data paths across NIC, host, and GPU memory, with focus on GPU connectivity (PCIe, NVLink, CXL)
Lead adoption of emerging standards such as UEC and UALink, while maintaining compatibility with existing ecosystems
Establish architecture guidelines and partitioning across hardware, firmware, and software
Drive performance modeling, analysis, and system-level optimization for AI workloads
Optimize scale-out communication patterns (e.g., collectives) for GenAI training and inference
Collaborate with software teams on drivers, runtimes, and integration with AI frameworks
Work with R&D, CTO, and peer architects on system definition and trade-offs
Engage with customers and partners to shape system requirements and use cases

Required SoC Vision Architect, Silicon, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a SoC Vision Architect in our Silicon team, you will be at the heart of defining the hardware that powers the next-generation of our products. You will bridge the gap between Artificial Intelligence (AI) research and physical silicon, architecting the Image Signal Processor (ISP), CODECS and the pixel data path. You will deliver unparalleled image quality while staying within the tight Power, Performance, and Area (PPA) constraints. You will participate in the concept, architecture, documentation, and implementation of a new product.
Responsibilities
Define a flexible imaging pipeline hardware architecture, from the sensor interface (e.g., Mobile Industry Processor Interface (MIPI)) through the ISP, the encoder/decoder, scaling and memory output.
Partner with our research to transform advanced computational imaging algorithms into high-efficiency hardware logic.
Conduct trade-off analyses between power, performance, and silicon area to meet thermal envelopes and current limitations.
Influence external executive vendor roadmaps, ensuring deep co-optimization between their future products and our custom silicon.
Lead collaboration across Architecture, Register-Transfer Level (RTL), Physical Design and Validation teams.

we are looking for a Senior CPU Core Architect.
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

We are seeking a highly skilled System Architect to join our growing team and play a key role in developing next generation automotive and IoT solutions. In this role, you will take end-to-end ownership of complex embedded systems, from high level architecture design to deep integration of vehicle-embedded sensors and advanced communication protocols.

Beyond technical excellence, we are looking for a forward thinking leader who can drive innovation evaluating emerging technologies, introducing AI driven capabilities, and shaping scalable, future ready architectures. You will actively influence product strategy, explore new approaches to performance optimization, cybersecurity, and edge intelligence, and lead the adoption of cutting edge MCU/SoC platforms and modern software methodologies.

If you are passionate about building high quality, reliable embedded software, pushing technological boundaries, and transforming ideas into robust real world automotive systems, wed love to meet you.

The Role
As part of System Architecture group, we are looking for an experienced System Architect to lead system and architecture for a network operating system of a hyper scale router & working as part of a technical team in charge of all system, software, algorithms and protocols design, Continues and constant customer engagement at the requirements, product and design levels.
Responsibilities
Collaborate closely with cross-functional teams including software engineers, network engineers, and product managers to define system requirements and design solutions.
Perform spec reviews and provide guidance to team members in design reviews
Develop and implement high-level design methodologies and standards to optimize system architecture.
Drive architectural initiatives that improve system resilience, security, and efficiency.