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Nuvoton Israel is a leading supplier of custom SoC and security hardware solutions for the computing and server markets. As a well-established and independent design center, we collaborate closely with top-tier customers such as HP, Dell, Qualcomm, Microsoft, and Google to develop advanced solutions that secure, control, and manage our customers platforms. We are seeking a talented and experienced Chip Architect to join our team. The ideal candidate is a self-motivated, fast learner with a strong background in hardware and system architecture. This role requires a technology leader capable of driving multidisciplinary programs and working closely with customers and internal teams across the entire product lifecycle. Responsibilities:
* Translate customer and marketing requirements into detailed SoC architectural specifications
* Provide functional specifications for chip hardware design and embedded software development
* Lead architectural decisions and serve as a technical authority across cross-functional teams
* Collaborate with customers and marketing to refine product requirements and align on technical solutions
* Support design, implementation, and verification processes throughout development
* Participate in system debugging, root-cause analysis, and issue resolution
* Support post-silicon bring-up, system integration, and software enablement

Required SoC Chip Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Chip Architect, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for our Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.
You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Cloud and our flagship AI services.
Responsibilities
Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software.
Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC).
Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency.
Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads.
Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.

Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

We are looking for a Chip Design micro architect for the Networking Silicon group. As a chip micro architect in our Networking business unit, you will join a group of passionate engineers to implement the next generation state-of-the-art BlueField DPU SOC and/or ConnectX NIC that deliver breakthrough networking, security, cloud, AI and storage performance to the AI data centers. As a design micro architect, you will make a real impact in a dynamic, technology-focused AI company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
You will be part of a small and exclusive micro-architecture team and have the opportunity to make a real impact in designing the micro-architecture of the next generation state of the art network card hand in hand with the product architect making sure implementation meets the product goals.
Work closely with architecture and design teams to thoroughly understand system requirements and identify micro-architecture solutions, while weighing trade-offs related to performance, area and power consumption.
Break high-level arch requirements into lower-level design building blocks. Focal point for the design team, reviewing implementation and guiding the team.
Find bottlenecks early in the development cycle using performance analysis and simulations.
Use your understanding of the entire chip and system to identify and debug pre and post silicon full-chip issues.

Requred SoC Power Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power Architect, you will not just design chips; you will define the energy efficiency of the infrastructure that powers our services worldwide.
In this role, you will be at the intersection of architecture, logic design, physical implementation, and system software. You will own the power architecture for next-generation custom SoCs (System on Chips), making critical trade-offs between performance, thermal constraints, and power delivery to build the most efficient computing platforms on the planet.
Responsibilities
Define and own the SoC power architecture, including complex power domains, clocking structures, and power delivery network (PDN) solutions to achieve optimal performance-per-watt.
Architect sophisticated power management policies, including dynamic voltage and frequency scaling (DVFS), power gating, and state strategies. Define the hardware/software interface for the Power management unit (PMU) and provide power management specifications.
Lead collaboration across architecture, RTL, physical design, packaging and validation teams to establish power budgets and specifications. Ensure power requirements are met from concept to tape-out.
Develop high-fidelity power and performance models to evaluate architectural features early in the design cycle. Drive pre-silicon power estimation and analysis to guide design decisions.
Lead post-silicon power analysis, correlating lab measurements with pre-silicon models to close the loop and improve future methodologies.

Required Senior HW architect
About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

We are looking for a hands-on engineer to join our Platform Architecture post-silicon team. This team analyzes and tunes the performance and power of Apple Silicon for the Mac, and takes the learnings and measurements to drive SoC architecture change for future chips. If you work comfortably across the hardware/software stack, and the idea to bring up brand-new chips that just arrived from the fab does not scare you but gets you excited, when we would like to hear from you.

You will join a multidisciplinary team of architecture, silicon design, and system software engineers driving the performance and energy efficiency of Apple SoCs. The work spans application software, system software, SoC architecture, and microarchitecture, and sits at the intersection of measured silicon behavior and forward-looking architecture definition. You will build a deep understanding of how current and planned Apple products behave end to end, and use it to influence both hardware and software direction.

Responsibilities
Tune and define SoC memory and fabric performance state controllers on unreleased silicon, and propose improved control and observability mechanisms for future generations.
Plan and execute architecture studies that drive performance and energy-efficiency decisions for future SoCs.
Build tools, workflows, and automation for repeatable analysis of simulated and measured data, including terabyte-scale traces from prototype devices.
Architect hardware features that improve workload characterization and enable robust online control of power and performance.
Debug complex interactions between system software and SoC hardware.
Assess the feasibility of future use cases, SoCs, and products.
Communicate findings across chip design, architecture, software, and system teams to enable data-driven decisions.

Required HW Architect team leader
About the Group
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact:
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing:
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

Required Micro-Architect, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Lead Design Activities at IPs, SubSystems(S.S) and SoC.
Define the block-level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up, as well as test plan development and coverage analysis for block and SOC-level verification.
Communicate and collaborate with multi-disciplined and multi-site teams.

We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!

Required Senior CPU Core Architect
Job Description
The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

Required Networking Silicon Architect, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a part of the team, you will define solutions for high-performance network accelerators and interconnects in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, with close collaborations with data center systems and Software teams. You will participate in the design, architecture, documentation, and implementation of the next generation of data center networking infrastructure.
You will be responsible for performance analysis for an end-to-end networking stack using your deep knowledge of high speed network infrastructure.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Evaluate different silicon solutions for executing our data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and advanced silicon integration technologies.
Design high-performance hardware/software interfaces.
Collaborate closely with system, software, verification, emulation, physical design, packaging, and silicon validation stakeholders to ensure that designs are complete, correct, and performant.
Drive vendor execution in various engagements: standard component roadmaps, build to specification, and co-developments.
Contribute to the evaluation of future ASIC designs and general architecture.

Required ML Hardware Achitect
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will help shape the future of Clouds next-generation AI infrastructure, architecting high-performance Machine Learning silicon designed to power hyperscale AI inference. You will have an opportunity to drive accelerator technology that powers Generative AI models, large language models (LLMs), and emerging agentic workloads where throughput, latency, memory bandwidth, and energy efficiency are mission-critical.
You will be part of a silicon architecture team pushing the boundaries of custom computing. Leveraging your deep expertise in hardware-software co-design, machine learning algorithms, and computer architecture, you will define and optimize custom compute engines and memory hierarchies that accelerate the world's most advanced AI models across Cloud datacenters.
Responsibilities
Lead the architectural definition, modeling, and specification of next-generation, high-performance ML compute IP and acceleration blocks for Cloud AI silicon.
Own the ML IP architecture specification throughout the entire product lifecycle: concept exploration, cycle-accurate modeling, implementation, silicon bring-up, and production.
Partner closely with leading AI research and algorithm teams (e.g., Google DeepMind, Gemini research teams) and software compiler teams (XLA, PyTorch) to explore architectural trade-offs and define hardware requirements for emerging model architectures.
Drive comprehensive architecture studies, evaluating compute dataflows, numerical formats, sparsity, and specialized acceleration mechanisms such as key-value (KV) cache optimization.
Drive performance, latency, power efficiency, and silicon area projections across model topologies and workload configurations.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

Lead the architecture and technical direction of a new product initiative
Design and build complex, high-performance systems from the ground up
Define core architectural principles, technology choices, and system design
Work hands-on on critical parts of the system and drive implementation
Establish high engineering standards (performance, reliability, scalability, code quality)
Drive technical decision-making in an ambiguous, fast-evolving environment
Collaborate closely with product and leadership to shape the product and its technical vision