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Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

seeking a Lead Networking Architect to help define and shape the next generation of our AI-SuperNIC scale-out chip.

Scale-out communication is a critical element in building competitive systems for modern data centers. Were looking for an expert with deep networking experience to collaborate closely with our AI/ML, platform and driver software, and VLSI teams in designing an optimized scale-out networking architecture.

If youre passionate about low-latency communication and have a strong background in RoCEv2, HPC communication, and NVMe-oF, this is a unique opportunity to take on a challenging and influential role.

This is a senior, high-impact position at the forefront of technology innovation-driving the development of cutting-edge networking and AI acceleration solutions.

Responsibilities

Work closely with CTO and peer architects to define the product requirements and features of next generation ultra low-latency AI-SuperNIC scale-out chip
Lead adoption of new industry standards such as UEC, UALink while maintaining a competitive solution for RoCEv2
Establish architecture guidelines, requirements, and the division of labor between software, firmware and hardware.
Lead performance estimations, modeling, measurements, and optimizations, as well as system-level integration efforts.
Engage directly with end customers and partners to shape use cases and system solutions.

The CPU Architect will take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We're looking for a hardware architect for our NIC and DPU division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our companys next generation NIC and DPU products. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.
What you'll be doing:
Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.
Define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
Define the implementation of debug capabilities to support performance validation and improvements
Understand our system debug requirements and help define the POR of our NIC and DPU product line.
Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
Thoroughly understand SoC flows, PCIe, Ethernet, InfiniBand and NvLink protocols.

We're looking for a hardware u/architect for our switch division. In this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of our next generation switch product lines performance, both Ethernet and InfiniBand. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design and platform teams to improve performance and debug.

What you'll be doing:

Learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and verification engineers.

Define the implementation of the most sophisticated performance features of our next products, balancing architecture requirements with backend, execution, and design considerations.

Define the implementation of debug capabilities to support performance validation and improvements

Understand our system requirement and help define the POR of our switch product line.

Face the most challenging Full-Chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.

Work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.

Thoroughly understand Ethernet, InfiniBand and NvLink protocols.

We are looking for a passionate and experienced software developer to join our Chip Design Technologies group, helping to build the software infrastructure and tools that shape the future of Chip Design and Verification. This role works at the intersection of infrastructure engineering, tooling, and database ownership. Youll be responsible for the backbone systems that enable the development of our industry-leading networking chips - the highway for the AI revolution.

We're looking for a senior hands-on engineer who combines deep expertise in Python automation and SQL data flows with a passion for large-scale compute environments. If youre excited about optimizing critical systems, owning the health of compute farms, and driving reliability across cross-functional teams, youll feel right at home here.

What youll be doing:

Partner with Chip Design teams to solve engineering bottlenecks: Collaborate closely with Design, Verification, and Methodology teams to identify workflow pain points and deliver infrastructure solutions that directly improve chip design productivity and quality.

Build automation infrastructure: Design, build, and maintain robust Python-based automation infrastructure that orchestrates chip design flows, monitoring, and infrastructure tooling.

Drive data integrity and performance: Own the MySQL/SQL schemas, migrations, and data integrity for our infrastructure tools. You will optimize queries and indexes to ensure our databases scale with our massive growth.

Own the platform health: Take ownership of the day-to-day health, capacity, and reliability of our compute farm and storage systems. This includes leading incident response, triage, and implementing long-term fixes to ensure high availability.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities:
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.
Act as Functional Safety manager, leading the definition, execution and oversight of functional safety strategy and processes-ensuring compliance with standards (such as ISO 26262), driving hazard and risk analyses, coordinating cross-functional teams, and embedding safety-culture across product development.

The CPU core Architect representative will be a member of the processor core architecture team. He will be responsible of the technical communication between the team in Israel and the team in China. He will be presenting and explaining Microarchitecture features developed by architects in Israel, collecting requirements, answering question. He will be responsible to hold deign reviews with the team in China. He will also be proposing new Micro architecture features based on his own ideas. take charge in defining a processor core that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products. The CPU core architect representative would be relocating to China for an extended period after getting familiar with the team in Israel.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Looking for a CPU Architect with expertise in HW/SW codesign of dense computational logic (e.g., vector, matrix)
The role includes but is not limited to:
Analysis of technical challenges in relevant use cases and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions in cooperation with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts.
(Preferably) models CPU functionality, performance and power in simulators.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

We are looking for a visionary and deeply technical Chief Architect for Data, AI & GenAI Platforms to drive the architecture, tooling, and long-term technological direction of our enterprise data and GAI products and initiatives. This is a foundational leadership role that sits at the intersection of hands-on system design, cross-functional enablement, and long-term strategic innovation.
You will serve as the chief architect and technology strategist across all data, AI, and GenAI efforts-owning the blueprint that powers intelligent products, agent-based experiences, and scalable platforms. Your work will influence product design, platform infrastructure, governance models, and the broader technical ecosystem we operate in.
We are seeking someone with deep, hands-on experience building large-scale, production-grade data and AI systems-combined with the ability to mentor teams, influence engineering leaders, and partner with product and business leadership to deliver enterprise-scale transformation.
Key Responsibilities
Define and own the technology vision, architecture, and evolution roadmap for all data, ML/AI, and GenAI systems across the organization.
Lead the architectural design and hands-on guidance of scalable data pipelines, real-time analytics, AI agent platforms, model hosting infrastructure, and enterprise knowledge frameworks.
Oversee and connect multiple AI and data-related initiatives, including LLM agents, vector databases, RAG pipelines, MLOps, and enterprise data lakes-ensuring coherence, reusability, and security.
Establish and enforce technical standards, patterns, and tooling across teams to ensure high-quality engineering, model performance, and platform scalability.
Partner with product, engineering, and business leaders to align technology strategy with product goals, business outcomes, and customer needs.
Guide the evaluation and adoption of emerging technologies including open-source GenAI frameworks, fine-tuning platforms, orchestration tools, and scalable cloud-native architectures.
Mentor and support principal engineers, data scientists, platform leads, and architects-creating a culture of technical excellence, experimentation, and ownership.
Champion data quality, model explainability, AI governance, and responsible AI practices across the entire lifecycle.
Serve as a senior thought leader internally and externally-representing the company in technical forums, conferences, and customer engagements when needed.

We are seeking an exceptional and experienced VP, Chief Architect to drive our overall architecture and technology strategy and execution. Reporting directly to the Chief Product and Technology Officer, this role will be instrumental in modernizing and scaling our platform to support product velocity, operational resilience, and future growth.
This is a highly cross-functional leadership role that requires deep technical acumen, architectural vision, and the ability to partner closely with Product, Engineering, and Executive teams.
Key Responsibilities:
Architecture & Technology Strategy:
Define and lead the companys architectural vision to ensure a scalable, modular, and high-performance product platform.
Partner with product and engineering leadership to align architecture and technology direction with business priorities.
Drive adoption of modern architectural practices and patterns across engineering teams.
Lead the evolution of the existing .NET monolith into a modular architecture that enables faster, safer development.
Anticipate future technology needs and ensure the platform evolves to meet growth and innovation goals.
Engineering Enablement:
Build frameworks, tools, and standards that accelerate development and reduce complexity for product teams.
Guide critical technical initiatives, serving as a senior advisor on platform-level architecture decisions.
Champion simplification, maintainability, and performance across all core systems.
Team Leadership:
Lead and mentor a high-performing team of architects and technology specialists.
Hire, grow, and retain top talent while fostering a culture of technical excellence, collaboration, and continuous improvement.
Act as a visible technology leader who inspires trust and credibility across the organization.

The Role
As part of System Architecture group, we are looking for an experienced System Architect to lead system and architecture for a network operating system of a hyper scale router & working as part of a technical team in charge of all system, software, algorithms and protocols design, Continues and constant customer engagement at the requirements, product and design levels.
Responsibilities
Collaborate closely with cross-functional teams including software engineers, network engineers, and product managers to define system requirements and design solutions.
Perform spec reviews and provide guidance to team members in design reviews
Develop and implement high-level design methodologies and standards to optimize system architecture.
Drive architectural initiatives that improve system resilience, security, and efficiency.