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We're looking for an energetic, hands-on Operations & Employee Experience Specialist to be the beating heart of our office and the go-to person who makes sure everything - and everyone - runs smoothly. This role blends day-to-day office management with a genuine passion for creating a great workplace culture. You'll be the person employees turn to, the one who anticipates needs before they arise, and the driving force behind a warm, organized, and fun work environment.

Responsibilities

Employee Experience
Own the full employee experience: company events, gifts, celebrations, employee onboarding.
Strengthen employees' connection to the company through thoughtful initiatives and touchpoints.
Plan and execute company events, holidays, birthdays, and milestone celebrations.
Build and maintain a warm, inclusive company culture.

Office Management
Manage the day-to-day running of the office: supplies, groceries/kitchen stock, parking, cleaning services, and maintenance as needed.
Serve as the main point of contact for vendors and service providers related to office operations.
Ensure the office is always a pleasant, functional, and welcoming space.

Travel & Executive Support
Book and coordinate flights and travel arrangements for employees and management.
Manage the CEO's calendar, including scheduling, prioritizing, and coordinating meetings.

Were looking for an enthusiastic and highly motivated Technical Support Engineer to identify, diagnose and resolve customers issues. The Technical Support Engineer will be a part of our Professional Services team.

This is an exciting opportunity to work in a challenging, fast-paced environment in a high-performance team. Here we truly put our people first. We strongly believe in teamwork, and we encourage and trust our people to reach higher, learn more, and live up to their potential.


Job Description
Taking ownership of customer issues reported by customers and prioritizing them based on urgency and importance.
Researching, diagnosing, troubleshooting issues and identifying solutions to resolve system issues.
Coordinating support case resolution with the appropriate internal teams: Sales, Professional Services, Product.
Following standard procedures for proper escalation of critical or unresolved issues.

As Chief Architect, you will lead cross-group technical efforts, head the Architect Guild, and lead the department's AI enablement and transformation efforts. You will serve as a technical consultant and see the large picture of technology stack and its architecture. Our technology stack is built to handle significant complexity, integrating advanced AI, Data Science, and algorithmic optimization with robust infrastructure - ranging from cloud-native K8s and Serverless deployments to specialized Mobile and Embedded systems

This is not a docs and slides position, were looking for an architect who wishes and can stay hands-on and be able to dive into multidisciplinary complex issues and independently solve them. You will work closely with R&D leads and engineers to ensure engineering best practices and excellence.

As a Drivers & Virtualization Engineer, you will own the host-facing software boundary. Your mission is to ensure our hardware is accessible, secure, and performant across diverse environments-ranging from bare-metal deployments to complex virtualized and multi-device cloud infrastructures. You will focus on building robust kernel-level interfaces where correctness, isolation, and long-term operational safety are paramount.

Responsibilities
Develop and maintain high-performance Linux kernel drivers for proprietary accelerator.

Implement communication protocols and virtual device interfaces to bridge hardware and software.

Manage low-level hardware interactions including PCIe, DMA, MMIO, and interrupt handling.

Enable seamless virtualized access to accelerators using QEMU and KVM.

Design and implement robust device sharing, passthrough, and isolation mechanisms.

Ensure the security of accelerator operations through strict memory protection and resource isolation.

Debug complex failures that span the entire stack: from hardware and kernel to hypervisor and guest OS.

Support the scaling of our architecture from single-device setups to large-scale multi-device deployments.

We're looking for a Senior Engineering Manager to lead our Data Platform group - owning the pipelines, storage, and streaming infrastructure, deployed on AWS, that power data-driven capabilities across the company, including an emerging AI agent for forensic data investigation.

Key Responsibilities:

Own end-to-end delivery for the group - roadmap, execution, and Agile/SAFe process.

Hire, mentor, and grow a team of engineers.

Guide architecture and technical direction for scalable data pipelines (real-time and batch), streaming (Kafka), and processing frameworks (Spark/Flink).

Oversee the platform's AWS infrastructure and cloud architecture decisions.

Ensure sound data storage design across relational, NoSQL, and search systems.

Drive improvements in reliability, observability, and cost efficiency.

Guide the team's development of an AI agent for forensic use cases, including MCP tool design for safe, effective data access.

Represent the group across a matrixed org and partner with product teams.

As a Senior Backend Engineer on the Exchange Engine team at our company, you will be a driving force behind the core systems of our massive mobile advertising platform. You will tackle complex architectural challenges where every millisecond counts, building real-time, highly concurrent systems that process millions of requests per minute. In this position, your impact extends beyond feature implementation; you will take charge of major initiatives, architect core systems, and raise the bar for engineering excellence across the entire team.
Key Responsibilities
Architectural Design & Execution: Lead the end-to-end design, development, and delivery of complex, scalable, and highly available backend services for our real-time ad exchange. Architect systems with a focus on long-term maintainability, ensuring that large-scale changes and migrations are predictable and low-risk.
Performance Optimization: Profile, tune, and optimize system performance to ensure ultra-low latency and high throughput under massive concurrent loads.
Technical Mentorship: Act as a technical multiplier by mentoring junior and mid-level engineers, conducting rigorous code reviews, shaping technical standards, and promoting software engineering best practices.
Cross-Functional Leadership: Collaborate directly with Product Managers, Data Scientists, and other engineering squads to translate complex business requirements into robust technical solutions and to understand the revenue journey, ensuring technical decisions directly support market competitiveness and platform growth.
Production Excellence: Own the lifecycle of your services in production. Implement advanced monitoring, alerting, and observability to troubleshoot and resolve deep-system production incidents.
Infrastructure Collaboration: Work closely with DevOps to optimize our deployment pipelines and cloud infrastructure (Kubernetes, GCP).
AI-Driven Engineering: Leverage modern AI coding assistants and agentic tools to accelerate development velocity, automate routine tasks, and free up cognitive load for complex architectural challenges.

As a Performance Software Engineer, you will be instrumental in building the core computation software that runs on custom AI accelerators. Your work will bridge the gap between host systems and proprietary hardware, encompassing everything from a custom on-board kernels to the sophisticated tooling required for real-time debugging. You will be a key player in chip bring-up and the long-term development of high-performance computation primitives and kernels, ensuring our architecture operates with maximum efficiency and deterministic performance.

Responsibilities
Develop and optimize low-level software primitives in C/C++, assembly, and architecture-specific intrinsics, primarily for RISC-V and ARM platforms.

Implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware operating in bare-metal or highly constrained environments.

Work closely with hardware architects and RTL/design teams to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.

Analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient use of processor and accelerator features.

Bring up and debug software on simulation, emulation, FPGA, and silicon platforms, including low-level hardware/software integration issues.

Develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality.

Contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.

The Head of C2 (Command & Control) Development will lead the design, development, and delivery of advanced control, monitoring, and decisionsupport capabilities for a nextgeneration defense system. This role requires a strong technical foundation in C2 architectures, realtime systems, and multisensor integration, combined with proven leadership experience in growing and guiding highperforming engineering teams.
Why Join us?:
This is a unique opportunity to be at the heart of a defense-tech startup during its most exciting growth phase.
Responsibilities:
* Lead a multidisciplinary development team with the ability to scale into a full C2 group as the program expands.
* Define the technical vision, architecture, and roadmap for our C2 subsystem, ensuring alignment with systemlevel requirements and operational needs.
* Drive endtoend development of control and monitoring capabilities, including situational awareness, mission management, data fusion, and operatorsystem interfaces.
* Collaborate closely with system engineering, algorithm teams, hardware teams, and operational experts to deliver robust, missionready solutions.
* Establish development methodologies, coding standards, integration processes, and Quality Assurance practices suitable for defensegrade systems.
* Mentor engineers, build team capabilities, and recruit additional talent as the group grows.
* Manage schedules, risks, and deliverables in a dynamic, multistakeholder environment.
* Interface with customers, partners, and defense organizations to understand operational constraints and ensure compliance with defense standards and regulations.

You'll work end-to-end: agent design, tool implementation, retrieval quality, integration into existing product UIs, cloud infrastructure, and evaluation/observability. The platform already ships to customers - you'll extend it, raise its quality bar, and help define where it goes next.

What you'll do

Design and evolve agents - build LLM agents with tool use, routing, and human-in-the-loop flows.
Implement tools and integrations - expose product capabilities to the agent, with multi-tenant context, via internal APIs and MCP servers.
Own retrieval quality - contribute to our RAG pipeline end-to-end: ingestion, embeddings, vector search, and reranking.
Define and evolve host integration contracts - collaborate with host application teams to integrate the assistant into product UIs built on different frontend stacks. You own the shared remote module and the integration API; host teams own their stacks.
Drive evaluation-led development - write evaluators (rule-based, LLM-as-judge, multi-turn), maintain CI eval gates, and use traces and feedback to debug production behavior.
Operate the platform - own deployments, observability, and the performance and cost of LLM-backed services.
Establish engineering practices** for AI-specific work: prompt versioning, eval coverage, testing, and code review.

Design high-performance analog and RF ICs optimized for precision, power, and area, driving prototype and product iterations from architecture to silicon validation.

Responsibilities
Design and simulate analog and RF integrated circuits, including critical blocks such as amplifiers, mixers, PLLs, ADCs, DACs, and bias/reference circuits, with a focus on signal integrity, linearity, and precision.

Optimize circuits for power, area, and performance trade-offs, ensuring designs meet system-level requirements across process, voltage, and temperature (PVT) variations.

Collaborate closely with optics, simulation and PCB teams to define architecture and block-level specifications for successive prototypes and product iterations, ensuring tight alignment with overall performance and integration goals.

Work with layout engineers to guide floor-planning and physical design, minimizing parasitic effects and preserving analog precision in layout-sensitive blocks.

Support post-silicon validation and bring-up, defining test plans, analyzing lab measurements, and correlating results with simulation to refine future design iterations.

Language: English at a proficient level. French is a plus.

In this role, you will lead all mechanical aspects of the product in R&D projects, taking it from concept to full scale development while working with multidisciplinary teams that include system engineering, physics, electronics, software, project managers, and others. You will serve as a technical focal point for mechanical design decisions, balancing performance, manufacturability, reliability, and cost.

Your role:

Lead the mechanical design including 3D models, drawings, prototype manufacturing, and production transfer.

Provide solutions that optimize performance, service, manufacturability, and cost.

Perform required analysis, testing, troubleshooting, and documentation.

Work with local and global teams inside and outside Philips to answer design, service, and production challenges.

Own mechanical risk identification, mitigation plans, and design reviews.

Operate in a multidisciplinary environment under conflicting constraints of performance, reliability, cost, and development schedule.

Play a critical role in ensuring the functional integrity, performance, and reliability of next-generation optical chips.

Responsibilities
Develop robust verification plans for complex digital and mixed-signal optical chip designs.

Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process.

Perform netlist-level simulations with SDF back-annotation for timing-accurate verification

Support FPGA/ASIC bring-up and post-silicon validation as needed

Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.

Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency.

Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers.

Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation.

Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams.

Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface custom tensor unit for advanced AI/ML applications.

Responsibilities
Design, implement, and verify RTL blocks for memory, control, and compute subsystems within custom multiphysics computation unit.

Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.

Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.

Support synthesis, timing analysis, and backend integration, working closely with physical design and CAD engineers.

Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of compute platform.

As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Responsibilities
Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.

Develop and optimize the digital backend flow.

Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).

Collaborate with front-end designers to address timing and logical/physical interface issues.

Support tapeout preparation and final signoff processes.