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We are seeking PHY Algorithm Technical Leader, Silicon One Israel
Meet the Team:
You will join the SerDes System Algorithm team within Silicon One High Speed in Israel, part of our silicon development organization. The team works across modem technology, system modeling, and signal processing for high-speed SerDes devices.
We are at the center of our ASIC group, building next-generation network devices for AI networks, the 5G era, and the future of routing. Our design center brings silicon hardware and software disciplines together in one site, combining a small-team startup atmosphere with the scale and stability.
Your Impact:
As a PHY Algorithm Technical Leader, you will provide technical leadership for the development, modeling, configuration, and optimization of algorithms for advanced SerDes modem systems. You will work with the latest silicon technologies and processes to help build large-scale, complex devices at the edge of feasibility.
Your work will contribute to Silicon One, a unified and programmable silicon architecture designed for service provider and web-scale markets. The role requires technical depth in digital signal processing, modem behavior, and using MATLAB for algorithm development, with the ability to guide algorithm work from initial concept through advanced SerDes system implementation.
Provide technical leadership for research, design, and development of PHY and modem algorithms for high-speed SerDes devices.
Define and use system models to analyze modem behavior, signal-processing performance, architecture constraints, and algorithm tradeoffs.
Guide modem configuration, tuning, and optimization to improve performance, robustness, and implementation feasibility.
Use MATLAB for algorithm development, simulation, testing, and data analysis.
Guide technical decisions, review algorithm tradeoffs, and mentor engineers on complex PHY and modem development tasks.
Lead cross-functional technical collaboration with system, silicon hardware, and software teams to move algorithms from modeling into practical implementation.
Support lab-based validation and debug activities when required.

We are seeking a skilled and experienced Software Engineer to develop a Go-based control plane within Kubernetes, with a focus on traffic security. You will be responsible for building and enhancing a Kubernetes-native control plane to provide seamless management of our eBPF datapath, enabling a secure traffic management in cloud and hybrid enterprise environments. You will work with a highly collaborative and skilled team to build solutions that advance the next generation of networking and security in Kubernetes environments.
Design and develop a Go-based control plane managing our enterprise-grade traffic security engine.
Develop APIs, tools, and custom resources to streamline secure traffic management, scaling, and failover within Kubernetes environments.
Debug, troubleshoot, and resolve performance, reliability, and security issues in the control and dataplane.
Participate in code reviews, architectural discussions, and contribute to technical documentation.

Required Tetragon Threat Detection Engineer - Isovalent
Job Description
About this role:
Cilium Tetragon is a flexible, Kubernetes-aware security tool, with real-time observability and enforcement. Leveraging the power of eBPF, Tetragon offers a low-overhead, in kernel solution that enhances security posture by monitoring system behaviors such as process executions, system call activities, and both network and file access events.
Tetragon Threat Detection Engineers primarily focus on creating and maintaining
Tetragon runtime security policies, based on the latest threat intelligence, vulnerability disclosures, and their own research.
Policies can act either as a mitigation to known vulnerabilities or as monitoring and protection against unknown security issues.
What youll do:
Develop and maintain Tetragon runtime security policies to ensure customers have good visibility of suspicious activity on their infrastructure and are protected against the latest emerging threats
Help design frameworks and architectures that allow customers to easily consume policies and understand their overall security posture
Monitor vulnerability disclosures (CVEs) and the latest threat intelligence to develop Tetragon runtime security policies
Work with software engineers at Isovalent and us to improve and enhance the capabilities of Tetragon security policies
Interact with solution architects and customers as necessary to support and deploy Tetragon security policies in production
Publish content and give talks based on your work.

The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics - all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners.

As a Senior Backend Engineer in the Data Management team, you will be instrumental in developing the core of our AI and data platform. You will design, develop, and maintain robust, high‑performance, and scalable backend services that support data‑driven and AI‑based solutions.

You will take part in solving complex technical challenges, optimizing system efficiency, and contributing to key architectural decisions that will shape the future of our platform. This role combines hands‑on backend development, deep problem‑solving, and close collaboration with cross‑functional teams.

You will:
Design, develop, and maintain scalable backend services for AI and data platforms.
Contribute to architecture and design decisions for distributed and high‑scale systems.
Build and maintain microservices and event‑driven systems.
Work with SQL and NoSQL databases to support data‑intensive workloads.
Debug, monitor, and improve production systems for performance and reliability.

Required Logic Design Engineer
Job Description
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.