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Required PHY Firmware Technical Leader
Meet the Team:
Join the Silicon One PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.
We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.
Your Impact:
Develop PHY firmware and system-level features for advanced networking ASICs
Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis
Collaborate closely with PHY, system, firmware, and silicon design teams
Contribute to defining system operation modes and end-to-end device behavior
Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies
Who Youll Work With:
The Silicon One group, the center of our ASIC design efforts
Cross-functional teams including silicon design, firmware, and system
Global teams working together to deliver game-changing networking devices.

Join us as a Product Lead - Data & ML on our Product Management team in Glil Yam to do the best work of your career and make a profound social impact.

As a Product Lead - Data & ML, you will be responsible for defining and delivering data-management and AI/MLOps capabilities within a data-intensive platform. You will work with cross-functional engineering, architecture, and external partner teams to drive advanced data and machine learning solutions that power enterprise-grade products.

You will:
Lead the full product lifecycle- from ideation and prioritization to design, planning, and delivery of AI/ML and data platform capabilities.
Define requirements and translate complex business needs into scalable product features in collaboration with engineering and architecture teams.
Drive MLOps and data platform initiatives, ensuring high-quality, production-ready solutions.
Collaborate with external clients and partners to deliver best-in-class solutions and align on product vision.

we are looking for a Bookkeeper.
Job Description:
Work within the finance department as part of the accounting team
Manage supplier and/or customer accounts
Perform bank reconciliations and issue invoices
Handle payments to suppliers and various additional tasks

As a Senior Software Architect, you will be responsible for defining the architecture and technical strategy of our SaaS and on prem platforms. You will work with multiple engineering teams on building scalable, secure, and high& performance data platforms that support enterprise AI workloads and mission critical applications.

You will:
Define and evolve architectural standards across security, data, and observability.
Collaborate with engineering teams to ensure cohesive and scalable system design.
Architect high scale services, APIs, and data pipelines for enterprise workloads.
Conduct architectural specifications review sessions (we work SDD and TDD), design workshops, and code level consultations.
Mentor engineers and lead architectural governance and design decisions.

Required Tetragon Senior Linux Security Engineer
About this role:
Cilium Tetragon is a flexible, Kubernetes-aware security tool, with real-time observability and enforcement. Leveraging the power of eBPF, Tetragon offers a low-overhead, in kernel solution that enhances security posture by monitoring system behaviors such as process executions, system call activities, and both network and file access events.
Tetragon Threat Detection Engineers primarily focus on creating and maintaining
Tetragon runtime security policies, based on the latest threat intelligence, vulnerability disclosures, and their own research.
Policies can act either as a mitigation to known vulnerabilities or as monitoring and protection against unknown security issues.
What youll do:
Develop and maintain Tetragon runtime security policies to ensure customers have good visibility of suspicious activity on their infrastructure and are protected against the latest emerging threats
Help design frameworks and architectures that allow customers to easily consume policies and understand their overall security posture
Monitor vulnerability disclosures (CVEs) and the latest threat intelligence to develop Tetragon runtime security policies
Work with software engineers at Isovalent and us to improve and enhance the capabilities of Tetragon security policies
Interact with solution architects and customers as necessary to support and deploy Tetragon security policies in production
Publish content and give talks based on your work.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.