לוח משרות דרושים חשמל ואלקטרוניקה

We are seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

Key job responsibilities
Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation - spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.

Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.

Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.

Engage with leadership: Communicate strategy, progress, and risk to senior leadership. Influence the overall silicon roadmap with analog capabilities and constraints.

We are looking for an Experienced HW SERDES Engineer to join Annapurnas SPIV (System Platform Interface validation) team.
As a member of the SPIV team, you will own End-to-end subset of system PCIe SERDES interfaces across range of products through product life cycle:
1. Validation and qualification.
2. Integration.
3. Deployment and post-deployment support.
4. Failure analysis.
5. Pre silicon activities for new technologies.
As owner, you will set the strategy for PCIe SERDES qualification over multiple platforms, ensure the design worked well and drive complex system debugs involving HW and FW components.

You will define NPI practices and engage in pre-silicon efforts to explore new technologies and mitigate integration risks. You will enhance SERDES qualification results with large scale customer performance analysis to discover SERDES life-cycle issues and mitigate them.

This is a fast-paced, intellectually challenging position, and you will work with thought leaders in multiple areas of technology. We are changing industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities
- Approve future products PCIe SERDES technologies.
- Define new products SERDES qualification and validation strategy and lead the execution.
- Engage integrations of Annapurna Labs products with other vendors PCIe HW components.
- Support ongoing integrations of PCIe SERDES in new products.
- Lead triage, PCIe SERDES debug and root cause analysis of systems in AWS data centers.
- Drive and maintain training, quality documentation and collateral to improve in-fleet operation.

We are looking for an energetic, detail-oriented individual to join our Data Center Engineering Operations Team. This committed group works to maintain the critical physical infrastructure that supports our Web Services. Specifically, this team works to ensure that the data center's MEP operates at 100% availability while maintaining first-class customer service to the teams and groups within the data centers.
The Data Center Engineering Operations Facility Engineer is responsible for operating and maintaining all electrical, mechanical, and fire/life safety equipment within the data center.
DCEO Facility Engineers are our front line responders for hands-on electrical and mechanical equipment troubleshooting and operation. This equipment includes, but is not limited to, stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers, cooling towers, chemical treatment systems, pumps, motors, VFDs, and building automation systems.

Key job responsibilities
- Operate and maintain mechanical and electrical equipment.
- Perform root cause analysis of equipment failures.
- Troubleshooting of facility and rack-level events within internal SLA.
- Ensure all safety procedures are adhered to while performing work.
- Able to work shifts (rotating work days during the weeks).
- Take daily operational readings of all mechanical and electrical equipment.
- Utilize internal CMMS to manage building workflows.

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.

The MLIL FLOW team is looking for a Senior Software Development Engineer to lead the design and delivery of systems software for our next-generation ML accelerator servers. We build production software to validate, initialize, monitor, and qualify these servers - from first silicon through fleet-scale deployment. We work on the physical systems that execute ML workloads: Server bring-up, hardware diagnostics, interconnect validation, power/thermal monitoring, and fleet-scale operations are our bread and butter.


Key job responsibilities
Lead the architecture and implementation of hardware validation and diagnostic software for new ML acceleration platforms.
Drive technical direction for PCIe validation, power/thermal diagnostics, and stress-testing frameworks that run across manufacturing, vetting, and production environments.
Own subsystems end-to-end: from design through implementation, testing, deployment, and operational excellence at fleet scale.
Work with Hardware, Manufacturing, EC2 teams to create coordinated software packages that enable both qualification and rapid deployment.
Debug and root-cause complex hardware/software interaction failures on first silicon and production fleet returns; drive root-cause to closure.
Build and maintain data pipelines, dashboards, and monitoring systems for fleet health and performance benchmarking.
Mentor engineers, define best practices, drive design reviews, and raise the bar for the team.
Lead multiple development initiatives in parallel, balancing schedule, risk, and technical quality across a fast-moving hardware program.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match - powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
- Micro-architecture definition.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities:
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

We are looking for a Junior Application Engineer to join a global team of Application Engineers that own a technical success and customer satisfaction across multiple high-impact projects.
Responsibilities
Provide close support to customers and deploy our technology across multiple projects
Provide training to customers on our tools and present our technology
Ability to plan, prioritize tasks/issues and take them to full resolution
Provide continuous feedback to R&D to improve the product.

We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Position location: in our Haifa or TLV offices, at least 2 working days at Haifa site (Hybrid model)
Responsibilities:
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.

We are looking to hire Embedded Software Engineering Students to join the SW group and take a major part in redefining the future of our cloud.

The Graviton SW team is looking for an Embedded Engineering Intern to join us in building next generation platforms. At the platforms team, you'll work on large and complex
boards, helping bring our Silicon devices into the fleet. You'll have the opportunity to learn about next gen platforms and contribute to the technologies that power the world's largest Cloud provider.

To Apply: Please submit your CV together with your updated grade sheet compressed into one pdf. Only applications with CVs & grades will be considered. Without both the CV and grades, we cannot consider your application.

We are looking for talented student to help us develop the semiconductor platform which is based on revolutionary architecture.
Take part in the development of products within disruptive system architecture.
Youll have the opportunity to work on the technologies that power the worlds largest Cloud provider, within a dynamic, open, and fast-paced environment.

We are looking for talented students to join the Verification team and help us technically lead the challenges of the next decade.

As a Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.