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we are now looking for a senior chip design rtl design engineer for the switch silicon group.
as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a combined design and verification team which develops some of the switch silicon core units.
plan and design rtl units / blocks according to arch & micro arch specifications under challenging constraints with high orientation to power, area, and performance.
build reference models, verify and simulate chip blocks/entities according to specifications.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.

this senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. its a unique opportunity to shape our technology and empower customers to build the supercomputers and ai fabrics of tomorrow.
what you'll be doing: lead the architectural design, development, and optimization of cutting-edge pcie firmware, using ai-driven modeling and insights to deliver exceptional performance.
serve as a trusted technical expert by investigating, debugging, and resolving challenging pcie firmware issues for our most important customers.
collaborate closely with our chip design, verification, software, and Architecture Engineers to find root causes and develop robust, long-term solutions.
champion the integration of ai-assisted diagnostics and generative ai tools across the entire development lifecycle to boost team productivity and innovation.
translate customer needs and field data into actionable feedback that directly shapes the future of our products.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

we are looking for an enthusiastic software engineer to join our ai networking acceleration team, to work on a groundbreaking open-source library, using hardware offloads, gpu kernels and rdma network cards. our product is a performance-oriented low-level infrastructure, crafted to change the way inference works.
we thrive as a team in a deeply strong environment, and we're passionate about innovation. the rewards are sweet and include working with some of the brightest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to collaborate on products that transform daily the way people work and play.
what you'll be doing:
developing a highly optimized inference framework
running on the worlds largest supercomputers and data centers.
the work environment is dynamic and challenging as our employees work on innovative, next-generation products at the forefront of technology in terms of performance, scalability, and features.

we are hiring a senior pcie firmware to the chip design pcie firmware team. you will be joining a team whose primary mission is to work on groundbreaking technology network adapters and build the core technology of the next generation devices in a wide range of fields - low-level C layer between hw and fws, automation challenges, and Python testing environment.
what youll be doing:
implement fw and verification features in a pre and post silicon environments in the pcie technology
collaborate with other teams in the pcie group, software, and architecture teams to define and craft legacy and new low-level firmware verification methods
improve the existing automated process

looking for a best-in-class chip design - hw emulation senior engineer to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in emulating our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. join world-class emulation team in israel. our focused team takes switches/nics/socs designs and program the emulators to behave like our silicon. are you ready to take on interesting problems and craft solutions? come check out our team.
what you will be doing:
the main responsibility is emulation and prototyping of complex chip designs. this includes defining the methodology and crafting the infrastructure needed to quickly take large chips into hardware emulation platforms.
the job also requires close collaboration with design, verification, and software engineers to enable Embedded software and application software development.
connecting emulator/fpga based solutions to real external h/w or virtual targets, taking care of complex testbench and different protocols.
this is a role for a versatile engineer that includes rtl design, verification, fpga partitioning and implementation, scripting, and lab-based bring up of the design.

seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

our company is looking for an asic design engineer to join the dft design team and develop the next generation dft technologies.
as a design engineer in the dft design team at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

seeking a highly skilled and modern software engineer to develop and prototype brand new advancements in distributed training and inference using nvidias spectrum-x ai fabric. this role offers a rare chance to pioneer ai and networking technology, contributing to ground-breaking projects that will define the landscape of large-scale ai systems. improve ai app-networking connection by refining communication, crafting congestion control, coding nic firmware, and expanding switch sdk features for enhanced ai factory efficiency. your work impacts large ai system development, scaling, and speed.
what youll be doing:
prototype end-to-end solutions to improve distributed training and disaggregated inference performance.
analyze and optimize communication flows across application, transport, and network layers.
develop system software spanning communication libraries, drivers, and firmware integrations.
collaborate with hardware, firmware, and sdk teams to co-design network features.
validate and integrate prototypes into nvidias ai infrastructure and products.

we are seeking an excellent Software manager to join to nvos  sw group in yokneam ilit. you will have the opportunity to lead a development team responsible for the software of the next-generation networking products while being hands-on with development activities. we drive the data growth of the worlds biggest companies. with dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. are you ready for the challenge?
what you'll be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the nvos .
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
support internal and external customers for any nvos related items.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the sw/fw relationship.
innovate! bring our networking products to shine in the customers view

our company is at the forefront of ai-driven innovation in vlsi design automation. join us to shape the future of semiconductor design with cutting-edge ai tools and make a significant impact in a collaborative, high-performance environment. are you ready to push the boundaries of whats possible in vlsi cad? come be part of our pioneering team!
what you'll be doing:
you will be responsible for developing and integrating advanced cad solutions and automation flows using ai and Machine Learning for vlsi design, verification, and implementation.
work closely with design, verification, and cad teams to identify areas for improving vlsi workflows using advanced tools and methods.
research, prototype, and deploy ai-based algorithms.
develop and maintain scripts and automation infrastructure to enable seamless adoption of ai tools in the vlsi design process.
continuously review emerging ai technologies and methodologies to keep our cad environment up-to-date.
provide Technical Support and training to engineering teams on ai-enabled cad flows and best practices.

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
at our networking, we are driven by innovation and excellence. our team in israel is looking for a dedicated chiplet layout owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing: be part of a cross-business-unit team and own the high-speed ip integration.
build a chiplet floorplan layout design from early assembly/planning through implementation and signoff.
work closely with partition owners and full chip sta engineers to assure high quality and timely convergence.
define and implement efficient, high-quality full chip/chiplet physical design tools, flows, and methodologies.
gain hands-on experience implementing the partition-level be design (rtl2gds).

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.