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We are seeking for an Information Security Implementer
This role requires CrowdStrike Falcon (EDR/XDR/IDP) - Ongoing management of the CrowdStrike platform, including defining protection policies, non-alerts, investigating security events on endpoints, identity protection management, and complex troubleshooting. AirWatch (MDM) - Management and operation of the VMware Workspace ONE (AirWatch) system for mobile device protection, security policy enforcement, application distribution and profile configuration. (CDR / File Whitening) - Operation and maintenance of inbound file whitening and sanitization systems, writing filtering policies, managing Multi-Scanning and Deep CDR processes. IBM Guardium - Application and operation of a database protection solution, access monitoring policy settings, auditing and controlling activities against sensitive databases. Cisco IronPort (Email Security) - Email protection system management, filtering policy settings, spam/phishing handling, blacklist/whitelist management and email traffic troubleshooting. Island Enterprise Browser - Implementation and management of a secure corporate browser, browsing policy definition, download and upload control, and DLP enforcement at the browser level. GoAnywhere MFT - Secure file transfer system management (managed file transfer), configuration of automated transfer processes, management of permissions and security protocols (SFTP, FTPS, HTTPS). Proxy / SWG products - Operation and management of proxy servers and Secure Web Gateway solutions, configuration of browsing policies, URL filtering, exception management and Internet traffic control.

As a Silicon Engineering Manager you will be responsible for improving silicon-photonics yield and performance through data-driven analysis, cross-functional collaboration and proactive issue resolution.

You will serve as the key interface between R&D, Process and Production teams, ensuring efficient data flow, rapid issue identification and continuous process improvement across wafer fabrication, device testing, and packaging stages.

Responsibilities
Perform silicon process and chip-level data analysis, establishing correlation between chip and wafer performance.
Lead process debug and yield loss analysis at chip/wafer level, driving root cause investigations and corrective actions.
Manage engineering approval forum to release production material.
Collaborate closely with vendors to implement new product tests and resolve technical/process issues.
Act as a key interface between design, testing, and production teams, ensuring alignment across the product lifecycle
Oversee and coordinate the transfer of data related to silicon design, testing, fabrication, and characterization between Production and R&D departments.
Develop and implement data management strategies to ensure data accuracy, security, and accessibility.
Maintain proper documentation of data transfer protocols, version control, and data integrity checks.
Support data analysis efforts to improve silicon performance, yield, and quality.
Ensure compliance with company policies and industry standards related to data security and confidentiality.

We are looking for a Photonics Layout Engineer to join our integrated photonics design team.

This position is also well-suited for Analog Layout Engineers who are interested in transitioning into photonic integrated circuit (PIC) design.

In this role, you will be responsible for creating, optimizing and validating PIC layouts, ensuring manufacturability, performance and compliance with foundry design rules.

You will work closely with device designers, process engineers and tape-out teams to deliver high-quality layouts of silicon photonics PICs.

Strong candidates will have hands-on experience with industry-standard layout tools, especially Cadence Virtuoso or similar software.

Understanding of photonic components, waveguide routing and automated layout generation is a major advantage.

You will also contribute to layout methodologies, PCells, and design automation flows to accelerate PIC development.

Responsibilities

Develop and implement mask layouts for photonic integrated circuits using Cadence Virtuoso or similar software.

Create and maintain PCells for photonic building blocks (waveguides, couplers, modulators, gratings, etc.).

Perform waveguide routing, ensuring correct connectivity, bend radius limits, and low-loss optical paths.

Verify layouts using DRC, and LVS to ensure compliance with foundry requirements.

Collaborate with device designers to translate basic schematics and specifications into Software schematics and manufacturable layouts.

Optimize layouts for performance, yield, and compactness while adhering to technology constraints.

Participate in photonic design automation tool development and workflow improvements.

Prepare and manage data for tape-out and support mask review processes.

Debug layout and rule-check issues and propose corrective actions.

We are seeking a hands-on Program Manager (PMO) to lead complex customer programs in a fast-growing, multidisciplinary deep-tech environment.

This role drives execution across customers, R&D and operations teams, owning programs from early design engagement through data centres qualification and production ramp - directly enabling customer adoption, predictable delivery, and revenue growth.

Responsibilities
Own end-to-end execution of customer programs - from design-in through DC qualification and production ramp.
Drive on-time delivery of milestones and customer commitments in complex technical environments.
Act as the execution focal point between customers, R&D and operations teams.
Build and scale multi-customer execution frameworks that support company growth.
Proactively identify risks, remove blockers, and minimize escalations across programs.
Ensure high-quality delivery while protecting engineering focus.

We are seeking a talented and motivated R&D Physicist to join our company.

In this role, you will be responsible for designing and carrying out experiments for SiPh chip performance and characterization, performing and analyzing laboratory experiments of chip level optical systems assembly, and developing and managing setups for photonics and laser devices characterization. In this roll you will be required to travel abroad for demonstrations and exhibitions as needed.

Responsibilities
Design and carry out experiments for SiPh chip performance and characterization.
Perform and analyze laboratory experiments of chip level optical systems assembly.
Develop and manage setups for photonics and laser devices characterization.
Provide technical support to the R&D team for experiments and data analysis.
Contribute to the development of new testing methodologies and techniques.
Ensure adherence to experimental protocols and safety procedures.
Maintain laboratory equipment and supplies.

We are looking for a Full Time Lab Technician to join our R&D team.

This is a full-time position with two evening shifts per week are required from 17:30-23:30.

Responsibilities

Identify and work with laboratory equipment, tools, supplies, and materials.

Maintain the lab area and equipment in a safe and organized manner.

Perform basic lab equipment maintenance as scheduled and in accordance with lab/equipment manual specifications.

Perform multiple concurrent tasks at several different equipment stations to maintain acceptable job flow.

Read, comprehend, and follow technical manuals and protocols.

Fill out all assigned reporting forms in a timely manner.

Read and interpret prescription specifications.