Lead SI analysis and modeling for high-speed digital interfaces such as SerDes.
Perform pre-layout and post-layout simulations using tools such as HFSS, ADS, HSPICE, Ansys SIwave, or Cadence Sigrity
Define stack-up, impedance targets, routing rules, and constraints to meet performance and compliance standards
Provide design guidelines and layout reviews for PCB and package teams to ensure SI integrity
Evaluate and model interconnects including vias, connectors, cables, backplanes, and packages
Support board bring-up and correlation of simulations with lab measurements using TDR, VNA, and high-bandwidth oscilloscopes
Drive root cause analysis and resolution of SI-related issues found in design validation or production
Develop documentation, standards, and best practices for high-speed design and SI analysis
Requirements: B.Sc. or M.Sc. in Electrical Engineering, Applied Physics, or a related field.
10+ years of experience in high-speed board design, SI modelling, and validation.
Expert knowledge of transmission line theory, crosstalk, reflections, jitter, and noise coupling.
Familiarity with power integrity concepts.
Experience in system -level timing and eye diagram analysis - Must.
Experience with multi-board systems, advanced packaging (BGA, SIP), and high-density interconnects is a plus.
Good English skills - Must.
This position is open to all candidates.