לוח משרות דרושים מהנדס מחשבים בפתח תקווה, לחיפוש זה נמצאו 4 משרות

As an Integration System Engineer in the Imaging Technologies team, you will own the end‑to‑end integration of a multidisciplinary medical device, from early design through validation and release.

You will lead system-level bring-up, define and execute integration strategies, and ensure robust interaction between mechanics, electronics, optics, and software.

This role emphasizes hands-on integration, performance analysis, and cross-functional alignment to deliver a high-quality, production-ready scanner.


Key Responsibilities

System Integration Ownership
Own system integration across all subsystems (mechanics, electronics, optics, software) and ensure a stable, testable, and scalable product.
Lead system bring-up, integration flows, and configuration management across development stages.
Identify interface gaps, define integration requirements, and drive closure with relevant teams.

Performance & Testing
Design and execute system-level experiments to evaluate performance, stability, and reliability.
Develop tools and automation for data collection, analysis, and debugging.
Define integration and verification test strategies, including acceptance criteria and coverage.

Problem Solving & Debug
Lead root-cause analysis of complex cross-domain issues.(HW/FW/SW/optics interactions).
Drive containment, corrective actions, and long-term fixes.
Ensure issues are resolved with clear documentation and learning capture.

Cross-Functional Leadership
Work closely with R&D disciplines, QA/RA, and manufacturing to align on system behavior and requirements.
Translate system-level needs into actionable specifications and integration plans.
Act as the technical focal point for integration-related decisions and trade-offs.

Process & Methodology
Establish and improve integration processes, methodologies, and best practices.
Introduce new tools, capabilities, and approaches to increase integration efficiency and quality.
Ensure proper documentation of integration flows, configurations, and test results.

Team Leadership & Mentorship
Mentor junior engineers and guide student contributors.
Assign and review tasks with a strong focus on quality, rigor, and engineering discipline.

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Which department will you join?
Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).