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Were growing fast, and our team is passionate about pushing AI engineering to new heights - solving complex problems in LLM training, inference optimization, reasoning, and agent orchestration at scale.
About the Role:
As a Machine Learning Engineer, youll work on cutting-edge
code-focused LLMs and AI agent systems
that power next-generation developer platform. Youll be at the center of research, model training, and productionization of intelligent systems that understand software deeply, collaborate with developers, and help automate engineering workflows end-to-end. Your work will immediately impact millions of engineers worldwide.
Responsibilities:
Push LLM Innovation: Research, design, and fine-tune domain-specific LLMs for code generation, refactoring, debugging, and multi-turn reasoning.
Agent-Oriented Development: Build multi-agent coding systems that integrate retrieval-augmented generation (RAG), code execution, testing, and tool use to create autonomous, context-aware coding workflows.
Production-Grade AI: Own the training-to-inference pipeline for large code models-optimize inference with quantization, distillation, and caching techniques.
Rapid Experimentation: Prototype and validate ideas quickly; leverage reinforcement learning, human feedback, and synthetic data generation to push accuracy and reasoning.
Cross-Functional Collaboration: Partner with product, engineering, and design teams to ship AI-powered features that help developers focus on high-impact work.
Scale the Platform: Contribute to distributed training, scalable serving systems, and GPU/TPU-efficient architectures for ultra-low-latency developer tools.

we are looking for a Senior Data Analyst.
As a Data Analyst you will be working with colleagues from various disciplines, such as - Product, Engineering, Marketing, Sales, Customer Success, Risk, Data Scientists within the team and other Data Analysts - on their KPIs, the way they observe information and the hardest questions each team is facing in order to drive insights and keep a data driven company.
You will play a key role in the ability of each team to keep scaling!
How your day is going to look, what you will be doing?
- Helping each team to take decisions based on data by:
Identify, analyze, and interpret trends or patterns in complex data sets to drive actionable insights
Define and implement KPIs across different teams
Accompany product features from tech design to feature performance
Translate product/business requirements to analytical logics, and create a very clear visualization which "tells the story" using a BI tool or other platform.

we are the next generation of multiplayer gaming uniting people around the gaming world in the most realistic way, face to face. At our company, you will be an essential part of the thinking and decision-making process behind our new product. As our Senior Game Economy Manager youll design and manage the in-game economy, track player experiences, and leverage behavioral insights, mathematical models, simulations, and data analysis to optimize KPIs and maximize player fun. (We work from our office in Tel-Aviv- not hybrid)


Responsibilities:


* Design, monitor, balance and lead the economy model and User Experience from an economy point of view to drive players' engagement and improvements in game KPIs
* Partnering closely with Product, LiveOps, Design, Analytics and Monetization to align strategy and execution.
* Model and balance complex systems in the game to maintain a healthy and growing in-game economy
* Control the pricing in the game - both for in-game currencies and real money
* Recommend and design reward systems and monetization features that fulfill player needs while meeting business goals.
* Perform data analysis and AB testing in order to always improve the game performance
* Monitor important in-game economic KPIs and maintain a balanced economy
#LI-Onsite

The Actuarial Department at our company is seeking a Financial Modeling Analyst to join a professional team that provides actuarial audit and advisory services to leading financial institutions in the market.
Our department works closely with public companies, banks, credit card companies, pension funds, and insurance firms, operating at the core of their economic and regulatory decision-making processes.
Key Responsibilities
Build, run, and analyze financial and actuarial models
Work with diverse databases, including developing and executing data controls
Create and maintain KPI reports and analytical deliverables
Collaborate with internal data servers and organizational information systems
Manage analytical tasks end-to-end while meeting deadlines
Work independently as well as in a team within a dynamic, challenging environment.

Join the Front-End Design team, at the core of our development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.

Your Impact:

Review micro-architecture specifications.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

About the Company A fast-growing deep-tech company is developing next-generation accelerated computing solutions for high-performance computing (HPC) and AI. The company designs a novel software-defined hardware architecture that enables significant performance, power, and scalability improvements for advanced compute platforms.
The organization values technical excellence, strong collaboration, and building technologies with real-world impact. The Role
We are looking for an experienced Physical Design team lead to lead and scale a physical design team responsible for complex, high-performance silicon. This role combines deep technical ownership with team leadership, and plays a key part in delivering cutting-edge compute platforms.
You will be responsible for driving the full physical design flow, mentoring engineers, and collaborating closely with cross-functional teams to achieve optimal performance, power, and area (PPA). Responsibilities
Lead a physical design team across all stages of the physical design flow, including floorplanning, placement, clock tree synthesis (CTS), routing, timing, and power optimization
Mentor and guide physical design engineers through block- and subsystem-level implementations
Drive technical direction and best practices for physical design methodologies and workflows
Collaborate closely with RTL, architecture, verification, and project management teams
Own timing analysis and closure, working with RTL teams to resolve timing violations
Ensure compliance with physical verification requirements, including DRC and LVS
Optimize designs to meet aggressive PPA targets and project milestones
Contribute to continuous improvement of design processes and execution quality

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Foundry, IP and Package Technologist, you will directly collaborate with architecture teams, external manufacturing partners (foundries and packaging vendors) to coordinate the technical stabilization and yield ramp of our custom silicon. You will be responsible for in-depth yield analysis, debugging process-design interactions, and driving corrective actions to resolve manufacturing defects. Your expertise in root-cause analysis and process optimization will ensures that our groundbreaking chips ramp up seamlessly from initial silicon arrival to high-volume production, directly enabling the future of our computing capacity.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Drive yield modeling for NPIs, support pre silicon activities in Foundry aspects of new devices.
Lead process debug investigations, utilizing inline data to isolate the root cause of yield limiters, distinguishing between random defects and systematic marginalities.
Drive yield improvements by executing advanced statistical analysis on high-volume manufacturing data, identifying subtle process-design interactions that impact performance, and defining the necessary corrective actions.
Collaborate with cross-functional design, product, and test teams to triage silicon failures, distinguishing between design bugs, foundry process marginalities, and packaging interaction issues to support New Product Introduction (NPI).
Partner with architecture and design teams to feed back critical manufacturing constraints into future product definitions, ensuring that next-generation chiplets are architected to be resilient to known process variances.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Design Verification Engineer, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure.
As part of our server chip design team, you will verify digital designs. You will collaborate closely with design and verification engineers on projects and perform direct verification. You will build efficient and effective constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.