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In this role, you will learn and deeply understand the AI fundamentals and create tools that simulate our companys AI neural network processor implementation.
In addition, you will perform in-depth analysis and optimization to the simulator, to ensure simulator performance and accuracy for various companys processors architectures.
The project is using C/C++ OOP as main development language as well as python for AI neural network.
Development platforms are Linux and Windows based.
Responsibilities:
Taking part of innovative, agile, top-notch Software organization, designing Neural Network Processor (NPU) simulator in close collaboration with the architecture, algorithms, system and hardware teams.
Design and develop simulation software solutions allowing our company customers to run most advanced AI networks efficiently on our company NPU software simulation.

In this role, as Embedded Software Team Leader, you will lead a team owning a key part of our company's NPU AI software stack, a complex, multi-layered system spanning the Host (SDK, runtime, APIs, and UMD/KMD drivers) and the NPU IP (embedded firmware). This stack is at the heart of the company AI software offering, with deep impact on multiple hardware and software teams ability to execute state of the art LLM, Generative AI and Neural Networks with extraordinary performance. Reporting to the AI Software SDK Senior Team Leader, you will lead a team of creative and result oriented enthusiasts that invent, design, and implement software that enables smooth connectivity between the NPU and Host CPU.
Responsibilities:
Lead and manage the Embedded Software engineering team, ensuring high performance and productivity.
Own the design, development, and implementation of your component within our company's NPU AI software stack, aligned with the AI Software SDK group's technical strategy, architecture, and roadmap and its automated CI and release process.
Collaborate with cross-functional teams to integrate solutions. Provide technical guidance and mentorship to team members.
Ensure project timelines and deliverables are met.
Conduct performance reviews and support professional development of team members.
Collaborate globally with architects, HW teams, NPU teams, and other developer teams.

In this role, you will design, optimize and develop features in the simulator.
Simulators are used daily by our architecture, algorithms, system, VLSI and QA teams - and by our company customers running the most advanced AI networks on our processors.
The development language is C/C++ (OOP) on Linux and Windows platforms.
Responsibilities:
Design and develop simulation software for our companys NPU and DSP platforms within an agile, top-notch software organization.
Perform in-depth analysis and optimization of simulator performance and accuracy across multiple our company processor architectures.
Dive into a large existing codebase to debug and deliver clever solutions to complex software challenges.
Interact and engage with architecture, algorithms, system, VLSI and QA teams, including remote design centers.

You will be a key contributor to our companys AI Graph Compiler software stack for NPUs, designing system-level execution flows for advanced neural networks, including LLMs.
The role focuses on L1/L2 memory management, data movement, and performance optimization, working closely with compiler and hardware architects.
What will you do:
Design and own key components of our companys AI Graph Compiler.
Develop and optimize neural network execution flows and memory management.
Enable complex AI workloads, including LLMs, and implement new NPU features.
Analyze performance bottlenecks and drive system-level optimizations.
Collaborate with compiler and hardware teams on HW-SW solutions.

In this role, you will build deep expertise in AI fundamentals, LLM and generative AI network architectures, and their underlying algorithms. You will continuously research emerging generative AI architectures across the industry, staying ahead of how the field evolves.
A central focus will be quantization - understanding, developing, and refining quantization methods and algorithms, and driving their deployment on our hardware to achieve maximum performance without compromising accuracy.
Responsibilities:
Explore and plan end to end network deployment on our company's hardware.
Own network accuracy measurement and improvement.
Develop the graph compiler's hardware-aware quantization tool.

In this role, you will have a direct impact on our product quality. As a team member in our SW team, you will be responsible for the development and operating of different SW and HW blocks in our system, analyze, optimize and debug your work and test the results and explore issues on your developed modules and other modules you will integrate with.
You will solve complicated failures and bugs and will dive into the code and the HW to understand why the failure occurs. You will be responsible for managing your developed products, including full test plan that will drive our system to zero bugs on the customer side
You will use the newest AI tools to speed up your development and debugging
Responsibilities:
Design, implement, maintain, optimize, and run various SW parts that are needed for the 5G Modem, including HW blocks drivers programming and operation.
Analyze and debug test results and explore results and issues.
Verify functionality and code performance of your developed code.
Track problematic code parts and work on improving them, WRT code cycle performance and code size performance.

We are looking for a CAD/Emulation Engineer to join our infrastructure team. This position is providing hands-on experience with advanced VLSI CAD/Emulation flows and infrastructure.
Key Responsibilities
Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and automation.
Support execution and releases of VLSI artifacts while maintaining advanced CAD flows.
Assist in improving infrastructure efficiency and tool integration.
Work with advanced version control systems and CI/CD pipelines for regression and build environments
Responsible for top notch emulation methodologies and procedures.

Lead a team of compiler engineers responsible for our company's open source based toolchain and graph compiler. You will be a hands-on team leader - driving architecture decisions, guiding engineers, and delivering compiler capabilities across all our company hardware targets. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for a leader who champions this approach.
Responsibilities
Lead development of our company's open source based toolchain targeting custom DSP and NPU architectures. Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation. Champion AI-agentic development practices within the team - integrating AI coding agents into day-to-day engineering workflows. Mentor engineers and conduct code reviews; build a high-quality engineering culture. Collaborate with hardware architecture, algorithms, and software teams globally. Own team planning, prioritization, and on-time delivery of toolchain features. Contribute hands-on to design, implementation, and performance tuning in C++ and Python.

The System team defines and develops cutting-edge 5G technology. In this role, you will lead the system team responsible for defining our next-generation modem products and developing modem algorithms, working at the intersection of research, system design, and implementation.
Responsibilities
Lead a team of senior system and algorithm engineers responsible for developing innovative 5G modems.
Partner closely with VLSI and SW teams implementing the modem HW and SW and align on system definitions with implementation constraints.
Develop and maintain deep expertise in cellular standards and their implications for modem design.
Lead system and algorithmic research, balancing trade-offs between DSP/SW/HW implementations, performance, implementation cost, real-time constraints, and time-to-market.
Own system definitions, requirements, and implementation from initial research through simulation to official release, including MATLAB/C/C++/SystemC modeling and specification documentation.
Mentor and grow team members, fostering technical excellence and professional development.

As a senior compiler engineer, you will own the design and development of our companys open source based toolchain and graph compiler. You will drive technical solutions end-to-end, deliver compiler capabilities across all our company hardware targets, and help mentor engineers. Our team embraces an AI-agentic development flow, leveraging AI coding agents to accelerate engineering productivity, and we are looking for engineers who champion this approach.
Responsibilities:
Design and develop our companys open source based toolchain targeting custom DSP and NPU architectures.
Drive design and delivery of graph compilation flows: transformations, operator mapping, and code generation.
Champion AI-agentic development practices - integrating AI coding agents into day-to-day engineering workflows.
Own complex components end-to-end, from architecture and design through implementation and delivery.
Provide technical guidance and mentorship to engineers; conduct code reviews.
Collaborate with hardware architecture, algorithms, and software teams globally.
Analyze and optimize toolchain output for performance and correctness across our company processor families.

In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.
This role allows for independent work, impactful input, and substantial contributions to the VLSI departments verification tasks
Responsibilities:
Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.
Collaborating with Design and Verification Teams.
Contribute to Verification Planning and Coverage.
Define formal verification plans, track progress, and contribute to achieving verification completeness.

Lead the development of our company Sensing SDK, a core software toolkit that integrates a broad set of computer vision, audio, and voice libraries, along with AI operators. The SDK is specifically designed and optimized for our companys latest NPUs and DSPs - NeuPro-M, NeuPro-Nano and SensPro2 - positioning it as a cornerstone of our companys sensing and AI platform.
Key Responsibilities:
Lead and mentor a team of software engineers developing our company Sensing AI SDK. Architect and implement high-performance sensing SW components for AI, vision, Audio and voice optimized for vectorize SIMD execution. Collaborate with compiler and DevOps teams to ensure efficient development and deployment. Drive technical excellence through code reviews, design discussions, and continuous improvement. Own the SDK roadmap, planning, and delivery cycles. Engage with customers to enable successful pre-sale processes, support integration and gather feedback.

As a Wireless Platform Architect, you will play a key role in defining the architecture of our company's next-generation Radio Subsystem (RSS) platforms for wireless technologies including Wi-Fi, Bluetooth and UWB. You will take end-to-end responsibility on the system-level architecture of a complete wireless communication subsystem, including system spec, requirements for implementation teams, definition of interfaces and testing concept.
You will work closely with multidisciplinary development teams and directly with customers, from early system architecture and trade-off analysis through implementation, integration, validation and productization.
Responsibilities:
Define the RSS end-to-end architecture and HW/SW partitioning, including interfaces between the radio, PHY, MAC, CPU/MCU, memories, PMU, clock and reset management (CRM) and other subsystem components.
Define architecture and operational mechanisms for multi-protocol operation and interoperability, including HW interfaces, state machines, control flows and operation sequences.
Define sleep/wake-up modes, testability, security and debug.
Drive PPA optimization and competitive benchmarking of the RSS, with particular focus on low-power operation, silicon area and overall system efficiency.
Work closely with RF, PHY/algorithm, HW, SW/firmware, verification and integration teams, from early system studies and architecture definition through RTL/FPGA validation and system bring-up.
Work directly with customers during technical engagements to define the RSS integration into their SoC and support customers throughout SoC integration, validation and productization, addressing system-level architecture, interoperability and integration challenges.

We are looking for an experienced physical-design leader who wants to remain close to technology while leading an accomplished engineering team.
You will lead a team of experienced backend engineers across Israel and India and own delivery across multiple projects in parallel.
This hands-on leadership role combines approximately 50% technical work and 50% team management, with end-to-end responsibility for turning complex RTL into tape out-ready GDSII.
Responsibilities:
Own and drive the complete RTL-to-GDSII flow, including synthesis, implementation, timing closure, physical verification, signoff, and tape out-ready IP delivery.
Lead, mentor, and develop a distributed team of experienced engineers while setting priorities and ensuring predictable, high-quality execution.
Provide hands-on leadership in flow development, advanced technology-node bring-up, integration, automation, and complex design closure.
Partner with architecture, frontend, verification, and other stakeholders to remove technical roadblocks and continuously improve backend methodologies.
The role includes working closely with customers and supporting backend convergence of the IP.

Join an agile team working on the most advanced wireless communication solutions, focused on the latest communication standards. You will define the architecture for future products and optimize modem solutions for hardware implementation.
Responsibilities:
Research and define architecture for advanced communication standards.
Define PHY System specifications and architecture for future solutions.
Define low-power architecture.
Work closely with the functional teams (Algorithm, HW/SW, RF, Validation, etc.), from early algorithm study to system validation.
Participate in integration and testing of wireless system solutions, spanning embedded SW, HW and radio.
Support customers engagement and product deployment.