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Which department will you join? our companys Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our companys future AI and deep learning HW accelerators. This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our companys EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like?
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

we are seeking a skilled Failure Analysis (FA) Engineer with expertise in X-ray inspection techniques to join our AV Platform team. The ideal candidate will specialize in using advanced X-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability
What will your job look like?
Perform detailed failure analysis using X-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
Interpret and analyze X-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
Develop and optimize X-ray inspection procedures and protocols for failure analysis and quality control.
Prepare test specimens: cutting, mounting, grinding, polishing and chemical etching
Collaborate with product engineering, quality assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
Prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
Support reliability testing and failure mode analysis for new and existing products.

our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments. This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems. This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

we are looking for a skilled and motivated Embedded SW Integration Team Lead for the Platform OS Department to manage the daily integration of the OS deliveries into our companys SW stack. The Platform OS team of we are leading a global effort of making the Linux OS as the Automotive Safety OS that will fuel the Autonomous Vehicle and the whole automotive industry. Youll lead a fast-paced, hands-on and dynamic team of integration and automation engineers, contributing to the overall qualification and integration effort of our company while collaborating with other teams across the organization.
What will your job look like:
Lead and mentor a team of 4-6 SW Integration and Automation engineers
Manage the daily integration of the aggregated delivery of all OS teams upstream into our companys SW stack.
Daily tracking of changes coming from OS development teams and controlling their integration order, priorities, test coverage and conflicts.
Managing a daily integration forum to track nightly tests reports, triaging new issues found and assigning them to development teams.
System level understanding of the OS features and tracking the test coverage developed by the OS developers.
Tracking the utilization, health and allocation of the HW resources in the farm.
Balancing test coverage to HW availability through tracking CI load.
Acting as a PoC for all OS integration issues. Both within the OS teams and externally.
Tracking bug escapes and their mitigation in the OS test coverage.

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products. We are looking for a talented and motivated Masters graduate in Electrical Engineering, with strong interest in Electromagnets and Microwaves, to join our Power Integrity team at our company.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities we are a single SI/EV team is another strong advantage, enabling joint simulation-measurements efforts.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Participate in the development of flows & methodologies from Synthesis , Place& Route & all signoff flows.
Plan & execute flow releases, coordinate & track development tasks.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new tools features and methodologies to bring innovation with significant RoI.
Hands-on physical design block ownership end to end, from Synthesis floor planning, Place & Route with target to achieve best PPA.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Serve as the technical lead while mentoring and guiding team members.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design CAD Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Lead the development of flows & methodologies from Synthesis, Place & Route & All signoff flows.
Plan & execute flow releases, coordinate & track development tasks between the team.
Exploration of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Serve as the technical lead while mentoring and guiding team members.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.
Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.
Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.
Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.
Servings as a technical expert while mentoring and guiding team members,
Hands-on physical design block owner from RTL to GDS , an option.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
Involved in the chip design & architecture definition for both functional & DFT domain.
Serve as the technical STA lead while mentoring and guiding team members.