דרושים » הנדסה » Master's Graduate in Electrical Engineering Signal and Power Integrity Team

You will join a team of talented and experienced Signal/Power Integrity (SI/PI) & Electrical Validation engineers with wide scope of responsibility, from Pre-Silicon SI/PI simulations to Post-Silicon Electrical validation and debugging, covering all High-Speed interfaces and Power Delivery of our company EyeQ ASIC products.
What will your job look like:
You will deal with design, simulations, optimization and debugging of high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, C/DPHY, Multi Giga-Bit Ethernet, High-Speed interfaces over Power Cables, Power Delivery Networks.
You will develop Layout guidelines, review the physical design process and check its quality.
You will deal with state-of-the-art signal & power integrity simulation tools and methodologies, advanced results analysis, optimization/verification of our company and customers' PCB designs, etc.
This is a dynamic work environment that requires interfacing with Silicon & Hardware design engineers, IP providers, Electrical and System Validation teams, Customer Application Engineers, EDA tools vendors, and product managers.
The proximity to Electrical Validation activities - we are a single SI/EV team - is another strong advantage, enabling joint simulation-measurements efforts.

our companys Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles. In our company, Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, and CDPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a relatively small team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our companys EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions, and automation, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

our companys Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles. In our company, Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5, PCIe Gen4/5, and CDPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a relatively small team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our companys EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions, and automation, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

our company's EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block or IP owner from RTL to GDS with horizontal domain ownership.
Collaboration with front-end and architecture teams to address issues, define design methodologies and improve QoR & convergence.
End to End ownership from Synthesis, DFT insertion, Floor Planning , Place & Route till signoff.
Signoff on all domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.
Exploratio of different methodologies from P&R till signoff to improve PPA & Turnaround time.
Evaluation of new technologies tools & features and to bring innovation with significant RoI.
Technical support and mentoring the engineers in the team.

The company's EyeC VLSI team designs chips for RADAR systems used in ADAS and autonomous vehicles. Our Physical Design team operates in a startup-like environment, emphasizing technical expertise, execution, and ownership. Each engineer in the Physical Design team takes full responsibility for their work, from initial definition through execution and final sign-offs. Engineers collaborate closely with design and architecture teams to develop constraints, conduct design reviews, and implement RTL modifications to ensure convergence. We are seeking an Experienced Backend to join our growing Physical Design team. In this role, you will play a key part in the design of state-of-the-art SoCs, from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS.
Floorplan exploration with guidance and collaboration with front-end and architecture teams.
STA: work with FE and floor planner to manage block and top level constraints and 1st level of timing analysis.
Synthesis exploration and final synthesis netlist: Scan insertion @ synthesis, clean checks from Lint, UPF & Spyglass.
Place & Route: from Synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Which department will you join? The SOC verification group owns the important and challenging job of verifying our company's chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments. This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems. This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

our company's EyeC VLSI team - a group designing the chips for RADAR systems for ADAS and autonomous cars. Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility . Each Physical Design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges Were looking for a Physical Design STA Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.
What will your job look like:
Leading FC timing activities & methodologies for brand New SoC, from definition to TO.
Writing design constraints (SDC) for FC/IP/Block levels for all modes.
Involved in chip architecture definition for functional & DFT domains.
Working in close collaboration with the front-end & architecture team.
Working with engineers to identify and overcome roadblocks and obstacles.
Defining AC timing from spec to implementation.
Supporting complex clock structures.

The RFIC/Analog design groups in our company's Radar organization is responsible for developing the cutting edge Transceivers in mmW frequencies for the best Imaging Radar technology. The design process includes the entire process from specs to productization. To support these challenging processes, we need a skilled CAD team that will work with the design teams on all design aspects and flows from design environment setups, through design tools implementations and support and to chip level verifications and validation enablement. We're looking for an Experienced CAD or Design Automation Engineer to develop our company's RF/Analog design tools/flows and automation flows for the next-generation Imaging Radar chips.
What will your job look like:
Build and support RF/analog design environments
Implement, develop, and maintain design flows, tools and scripts.
Evaluate and explore new automation technologies and advocate for efficiency improvements
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs
Effectively communicate and support a large number of designers, providing high-quality tools and flows, documentation, and presentations.

As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.

Responsibilities:

Understanding the high-level specification and requirements of functional units of micro-controller and application processor products.

Define the Micro-architecture for an unit and developing its RTL, including all design stages.

Collaborate with verification team on the test plan development for the blocks and verification closure.

Analyze synthesis/timing reports, identify and address critical areas to meet the PPA targets.