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In this role you'll design and build features that shape how customers discover products - tailored to their preferences, helping them find exactly what they need, even before they know they need it. We're defining how LLMs integrate into real-time personalization, how noisy behavioral signals become durable customer understanding, and how AI-powered experiences ship reliably at scale. You'll work across multiple technical teams, ship iteratively, and see your work in the hands of customers quickly. This organization values experimentation, moves fast, and gives engineers real ownership over what they build.

We are looking for a Software Development Engineer with sound technical judgment and a bias for action who takes ownership of problems end to end, communicates clearly, and cares about operational excellence - not just launching features, but making sure they hold up at scale. Someone who naturally raises the bar for the team: mentoring junior developers, advocating engineering best practices, and thinking beyond the immediate sprint.

Key job responsibilities
- Design, build, test, and operate production AI features used by multiple teams and operating in our scale.
- Deliver end-to-end solutions with focus on maintainability, scalability, performance, and reliability.
- Collaborate with Product and Science to define experiences, run experiments, and iterate based on data.
- Build AI-powered experiences including personalized recommendations, relevance explanations, and knowledge-driven features using LLMs and generative AI.
- Define and implement measurement strategies including analytics events and experiment configurations to track engagement and retention.
- Navigate ambiguity and make sound technical decisions in a problem space where established patterns don't always apply.

We are seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

Key job responsibilities
Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation - spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.

Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.

Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.

Engage with leadership: Communicate strategy, progress, and risk to senior leadership. Influence the overall silicon roadmap with analog capabilities and constraints.

We are looking for an Experienced HW SERDES Engineer to join Annapurnas SPIV (System Platform Interface validation) team.
As a member of the SPIV team, you will own End-to-end subset of system PCIe SERDES interfaces across range of products through product life cycle:
1. Validation and qualification.
2. Integration.
3. Deployment and post-deployment support.
4. Failure analysis.
5. Pre silicon activities for new technologies.
As owner, you will set the strategy for PCIe SERDES qualification over multiple platforms, ensure the design worked well and drive complex system debugs involving HW and FW components.

You will define NPI practices and engage in pre-silicon efforts to explore new technologies and mitigate integration risks. You will enhance SERDES qualification results with large scale customer performance analysis to discover SERDES life-cycle issues and mitigate them.

This is a fast-paced, intellectually challenging position, and you will work with thought leaders in multiple areas of technology. We are changing industry, and we want individuals who are ready for this challenge and want to reach beyond what is possible today.

Key job responsibilities
- Approve future products PCIe SERDES technologies.
- Define new products SERDES qualification and validation strategy and lead the execution.
- Engage integrations of Annapurna Labs products with other vendors PCIe HW components.
- Support ongoing integrations of PCIe SERDES in new products.
- Lead triage, PCIe SERDES debug and root cause analysis of systems in AWS data centers.
- Drive and maintain training, quality documentation and collateral to improve in-fleet operation.

We are looking for System Software Engineer to help define, shape, and integrate advanced solutions for the next generation of our cloud platforms.

Join our dynamic System Software team in creating innovative software solutions that power our product development lifecycle from conception to deployment. You'll develop critical tools that ensure product excellence across design, validation, manufacturing, and production environments


Key job responsibilities
Design and develop software tools for all product development stages (card level, rack level).
Collaborate with hardware engineers, firmware developers, and system architects.
Create and maintain debugging tools and utilities
Develop comprehensive documentation and provide training for tools.
Optimize testing and validation processes for coverage, speed, efficiency, and resource utilization.
Research and implement new technologies to enhance the testing ecosystem.
Support critical system troubleshooting and issue resolution.
Participate in design reviews and provide technical guidance on testability.

Come join the Agentic AI science team in building the next generation models for intelligent automation.

We are looking for world class researchers with experience in one or more of the following areas - autonomous agents, API orchestration, Planning, large multimodal models (especially vision-language models), reinforcement learning (RL) and sequential decision making.

We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match - powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
- Micro-architecture definition.
- RTL coding and debug.
- Synthesis and timing closure.
- Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

We are looking for a SoC / IP Architect to shape the next revolution in electronics!
Responsibilities
Define and design architecture: Create the overall SoC/IP architecture based on product and customer requirements and define detailed technical specifications.
Collaborate with cross-functional teams: Work with a variety of teams, including logic design, verification, firmware architecture and development teams, and physical design, to ensure successful execution.
Lead technical discussions and architectural reviews, guiding design and verification teams to deliver scalable, high-quality implementations.
System-level integration: Ensure seamless hardware-software co-design by working on aspects like control paths, interrupt schemes, and debug infrastructure.
Drive architectural decisions that optimize scalability, and future readiness for next-generation applications.

We are seeking an Applied Scientist to help build our next-generation customer memory and personalization systems.

As an Applied Scientist, you will design and build ML and LLM-powered solutions for our customer memory and personalization systems. You will work on how customer knowledge is extracted, validated, and applied in production systems.

You will own the end-to-end delivery of ML solutions, from problem formulation and modeling to offline and online experimentation, and production deployment at scale. You will deliver high-quality, scalable systems that power customer-facing experiences.
You will drive work across areas such as fact extraction, memory quality and lifecycle, temporal reasoning, and grounded personalization, while navigating tradeoffs between quality, latency, and coverage.
You will collaborate closely with engineering and product teams to translate research into measurable customer impact.

We are seeking an Applied Scientist to help build our next-generation customer memory and personalization systems.

As an Applied Scientist, you will design and build ML and LLM-powered solutions for our customer memory and personalization systems. You will work on how customer knowledge is extracted, validated, and applied in production systems.

You will own the end-to-end delivery of ML solutions, from problem formulation and modeling to offline and online experimentation, and production deployment at scale. You will deliver high-quality, scalable systems that power customer-facing experiences.
You will drive work across areas such as fact extraction, memory quality and lifecycle, temporal reasoning, and grounded personalization, while navigating tradeoffs between quality, latency, and coverage.
You will collaborate closely with engineering and product teams to translate research into measurable customer impact.

We are looking for a Senior ASIC Physical Design Engineer to join our dynamic team, Join the ride as we spearhead the next revolution in electronics!
What Youll Do
Own and continuously improve our smooth product backend integration methodology, flows, and best practices using Cadence and Synopsys tools.
Develop, maintain, and scale automation and infrastructure (TCL / Python) to improve quality, predictability, and turnaround time.
Collaborate closely with multiple teams to ensure smooth handoffs and high-quality product.
Support field teams on complex technical issues when needed.
Responsibilities:
Implementation of ASIC units using advanced flows
Developing BackEnd methodology using Cadence and Synopsys tools
Build and develop scripts for physical design implementation
Support Field team with customer issues.