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as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

We are looking for a skilled and motivated experienced rt systems integration & release manager to lead an systems integration team and own the end-to-end integration and release process for Real-Time Embedded products. this role is responsible for defining integration workflows, managing team execution, and ensuring that system releases are stable, predictable, and aligned with quality and delivery commitments.
the ideal candidate combines deep Embedded systems expertise, strong people leadership, and disciplined release and process management. what will your job look like:
directly manage and mentor a team of  rt systems integration and release engineers.
define, implement, and continuously improve the rt system integration and release management processes.
establish standard workflows, best practices, documentation, and quality gates.
ensure consistent execution of integration activities across projects.
drive alignment to integration processes across firmware, software, hardware, QA, and system validation teams.
identify integration risks early and implement mitigation strategies.
lead system -level integration of  Real-Time hardware and software.
manage system debugging, and root-cause analysis of complex integration issues.
oversee validation, verification, and system -level testing activities.
communicate progress, risks, and mitigation strategies to stakeholders and leadership.

we are the production TEST team - responsible for the definition, development, and deployment of production TEST operations for the worlds most advanced socs for adas and self-driving vehicles.
this is your opportunity to join a team during its initial forming stage and leave your mark as our company assumes full ownership for its silicon production operations to enable high volume manufacturing for cutting-edge automotive products. what will your job look like?
work closely with the design teams from early stages of the design process to review dfx architecture and define TEST requirements.
define TEST methodologies and generate TEST content for high-speed interfaces of Embedded ip blocks (lpddr4/5, pcie gen4/5, d/ C /mphy).
TEST program coding, pattern conversion and pre-si validation (virtual TEST simulations)
support load board and probe card design activities.
lead post-si TEST program debug activities to enable delivery of samples to internal and external customers.
TEST program characterization and tuning to enhance TEST program quality to meet automotive standards.
support quality & reliability team to enable effective and timely qual plan execution.
lead TEST deployment activities with tier-one foundry and osat vendors to enable large-scale wafer-sort and final- TEST operations.

we are software group is looking for an experienced Python infrastructure tech lead to join our software infrastructure team. our group is responsible for the full software stack running in the vehicle, as well as the development tools and infrastructure that support it. we build and maintain a large-scale automation and infrastructure platform that serves multiple engineering teams across. in this role, you will lead the architecture, design, development, and maintenance of high-quality Python -based infrastructure and applications. you will collaborate closely with software engineers, system architects, and project stakeholders to deliver robust, scalable, and innovative solutions that directly impact core automotive technologies. what will your job look like?
lead technical improvements and proactively enhance system performance, scalability, and Developer productivity.
take ownership of system architecture and technical design, from high-level design to implementation.
collaborate with cross-functional teams to define, design, and ship new features.
develop and maintain Python applications for various projects.
optimize applications for maximum speed.
write clean, efficient, and well-documented code.
troubleshoot and debug issues as they arise.
stay up-to-date with the latest industry trends and best practices.
help shape a structured, collaborative, and improvement-driven engineering culture.

we are looking for a software integration team lead to join our av group and lead sw deployment and integration for next-generation av platforms. what will your job look like?
lead a team of software integrators responsible for deployment & integration of dedicated sw & hw toward av validation campaigns.
serve as the focal point for platform sw technical challenges in the areas of Embedded sw, Linux, logging platforms, and hw/sw integration toward validation.
drive technical direction, task prioritization, execution planning, and delivery of integration milestones.
collaborate closely with internal & external engineering and validation teams to resolve complex multidisciplinary technical issues, while mentoring and developing team members.
act as an integral part of the platform development leadership in a dynamic, solution-oriented environment.

our eyeq platform group (epg) is seeking a motivated formal Verification engineer to join our team and contribute to development of hardware verification environments.
this position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
this is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle. what will your job look like:
be the owner of formal verification environment from first draft to sign-off stage
apply formal methods to verify the correctness of various complex digital systems
work with hw architects/designers to define assumptions, rules and cover properties
help define the formal verification methodology and environment to be applied by the team
explore new formal methods and tools
work with tools like cadence jaspergold, verisium manager, xcelium, indago
analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
develop generic formal blocks/functions of commonly used logic, to be later used off the shelf

we are looking for a senior pcb design layout engineer to join our hardware engineering team at the autonomous vehicle platform department as a key player in the development of next-generation ecu (electrical control unit) for autonomous vehicles. what will your job look like?
working closely with hardware and mechanical design engineers, you'll perform pcb layout our ecus and other products.
complete development of cad layout from footprint definition, detailed component placement, constraints management, with a concept of topology and signal and power integrity.
be responsible for the design releases required generation of artwork files, odb++, fab drawings, ict report, and electronic pcb documentation.
your designs will need to follow ipc class 3, signal and power integrity constraints, emi/rfi control and automotive regulations.

the operating system team is looking for a highly talented Embedded sw integration engineer with a passion for operating systems and Linux in specific.
the team is developing the boot and operating system sw for autonomous vehicle and smart advanced driver assist platforms. what will your job look like?
hands-on debugging and testing of os and related components (boot, hw initialization, device drivers, Linux Kernel, user space libraries and tools & automated tests in Python ).
deep understanding of the involved os/boot components and their integration with other sw/hw modules involving testing automation and system level validation.
closely work with members of the boot and os development teams to integrate, TEST and automate new features, components and systems.
release & feature management in a multi-project and multi-disciplinary environment while managing ci systems for testing coverage.

join our rem (road experience management) department - the team driving the automatic creation of high-definition maps, a cornerstone technology behind our autonomous driving and advanced driver-assistance systems. rem map creation leverages cutting-edge algorithms executed at massive scale using Big Data technologies, requiring both a deep understanding of the map creation pipeline and strong technical expertise. you will be part of our priority semantics algorithmic team, focused on understanding right-of-way rules and interactions derived from traffic signs, road structures, and driving behavior.
the team uses cutting-edge technologies, including graph neural networks (gnns) and data -driven learning techniques, to model complex driving scenarios and extract meaningful insights from large-scale real-world driving data.
this role requires a deep understanding of the data itself, modeling complex semantics, and extracting insights using learning-based approaches to accurately represent real-world driving priorities.
what will your job look like?
design, train, and evaluate cutting-edge deep learning models on rem proprietary map data
perform high-scale, large-volume data analysis
integrate new map-based algorithms with full ownership
develop tools that enable fast and effective data introspection
optimize models and results where needed.

We are the world leader in automotive and driving assistance systems, developing the world's most advanced software technologies and hardware architectures.
our group is located in haifa and is responsible for enabling the deep learning and computer vision algorithms on the platform. the technology we develop enables state-of-the-art deep neural networks to run efficiently in vehicles - contributing to saving lives and enabling autonomous vehicles. this is an exciting opportunity to work with highly talented engineers and be a part of a product with a lot of innovation and work on cutting-edge compiler and optimization technologies in the ai domain.
what will your job look like?
shape our product by applying cutting-edge deep learning network optimization techniques and will have the chance to influence future generations of our hardware and software
develop a deep learning compiler stack that takes neural network descriptions created in frameworks such as tensorflow and pytorch and converts them into code suitable for execution on custom-built our hardware
use state-of-the-art open-source technologies such as mlir and work closely with the open-source community
develop optimized implementations of a variety of neural-network operations and new optimization techniques and algorithms to efficiently map ml models onto our state-of-the-art systems
develop a toolchain that will provide a quantum leap in deep learning capabilities and performance.

we are seeking a skilled failure analysis (fa) engineer with expertise in x-ray inspection techniques to join our av platform team. the ideal candidate will specialize in using advanced x-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability what will your job look like?
perform detailed failure analysis using x-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
interpret and analyze x-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
develop and optimize x-ray inspection procedures and protocols for failure analysis and quality control.
prepare TEST specimens: cutting, mounting, grinding, polishing and chemical etching
collaborate with product engineering, Quality Assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
support reliability testing and failure mode analysis for new and existing products.

Our SOC verification group owns the important and challenging job of verifying mobileye's chip. it is involved from product specification to final SOC delivery, and involves all the system components. the group is made up of few of the best Verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
what will your job look like:
you'll be responsible for pre-silicon system -level verification of the most cutting-edge ai accelerators and technologies in the automotive field.
define the testplan, develop and run tests on simulation/emulation environments, develop TEST environment and verification collaterals.
you'll have a broad effect on our unique product from the very beginning of the process.

which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

we are a multidisciplinary development team working on a cutting-edge autonomous driving project, at the forefront of automotive technology. the team develops complex ecus that combine multiple socs, low-level firmware, hardware, validation, and automation systems, enabling next-generation autonomous capabilities. we work closely with hardware, system, verification, and automation groups to bring up, debug, and validate advanced automotive platforms from early development stages through production. this is a highly technical, hands-on environment focused on solving real system -level challenges.
what will your job look like:
debug complex hw/fw and system -level issues in an autonomous vehicle platform
perform deep root-cause analysis across firmware, hardware, and automation systems
lead firmware bring-up, integration, and debug of ecus with multiple socs
debug and support automation systems, including lab automation and fw verification environments
analyze failures originating from automated TEST systems and distinguish between fw, hw, and TEST infrastructure issues
work closely with hw, system, validation, automation, and architecture teams
support issues from early development stages through production and field failures
contribute to firmware debug methodologies and verification strategies
provide technical leadership and mentoring when needed.

which department will you join?
epg is a fast-paced, dynamic, and startup-like group responsible for researching, incubating and developing next-generation technologies and ideas, with a strong orientation towards computer vision, Machine Learning, data, and ai.
the group hosts a diverse team of scientists, engineers and developers to research, realize, and bring to market innovative new products, leveraging cutting-edge technologies, skills and capabilities.
were looking for a backend expert to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out.
what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.