דרושים » חומרה » CPU Memory Performance Architect

We are looking for a Principal Engineer with deep expertise in database internals, system architecture, and hardware-aware performance optimization.
This role is responsible for defining and driving advanced database performance solutions by understanding and improving the interaction between database engines, operating systems, and modern hardware architectures.
The ideal candidate is an experienced technical leader with a strong background in database systems, performance engineering, and computer architecture. The candidate should be capable of leading complex technical initiatives, influencing architectural decisions, and developing innovative solutions for next-generation database platforms.
This is a hands-on technical leadership role requiring expertise across database kernels, query execution, transaction processing, memory systems, and low-level performance optimization.

Responsibilities
Define and drive technical direction for database performance optimization and hardware-aware database architecture.
Lead the design and implementation of advanced database optimizations focused on scalability, efficiency, and workload performance.
Solve complex performance challenges across the full system stack, including database engines, query execution, transaction processing, concurrency control, storage engines, operating systems, and hardware platforms.
Design and develop optimizations leveraging modern hardware architectures, including multi-core CPUs, large-memory systems, NUMA platforms, CXL memory, RDMA networking, and advanced storage technologies.
Improve database execution engines, caching mechanisms, memory management, storage systems, and workload scheduling.
Analyze system behavior and identify bottlenecks using profiling, tracing, hardware performance counters, and low-level performance analysis.
Develop benchmarks, workload models, and methodologies to evaluate scalability, efficiency, and architectural tradeoffs.
Collaborate with database kernel, infrastructure, and engineering teams to influence architecture decisions and deliver high-impact improvements.
Mentor senior engineers and contribute to building technical expertise across the organization.
Drive innovation through research, prototyping, technical analysis, and architectural improvements.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

We are looking for engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle.

As a CPU Verification Engineer on the Graviton team, you will be responsible for verifying the correctness, performance, and robustness of our next-generation ARM CPU cores and their surrounding subsystems. You'll work at the intersection of micro-architecture, system architecture, and software - ensuring our CPUs meet the highest quality bar before they reach silicon.

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next-generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage, and networking at large scale. We aim to drive innovation and deliver software-defined infrastructure and algorithms for HPC, AI/ML, and Big Data applications.
We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.

What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software.
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU).
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale.
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations.
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads.
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions.
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally.
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction.
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems.

Our Autonomous Driving software group is looking for a Linux kernel expert with deep knowledge in the PCIe standard. As a Linux Kernel PCIe Architect, you will be part of the OS Architecture team and will be responsible to define the operating system solutions based on the PCIe standard for connectivity with peripherals and as an interconnect between multiple EyeQ SoCs.
This is an exciting and unique opportunity to work with highly talented Linux OS architecture and developments teams and be a leader in the definition of the cutting-edge technology for the Automotive AI applications.
What will your job look like?
Researching and defining the SW solutions based on the PCIe standard and the Linux implementation for the PCIe stack
Designing and Implementing the SW Stack for the communication between the EyeQ SoCs laying the infrastructure for cross chip neural networks.
Defining the future HW solutions by working closely with the SoC Architecture team in a SW/HW co-development environment.
Performing performance analysis, feasibility studies, PoCs and optimization flows to achieve the highest performance with minimal resources.
Work closely with the Linux Kernel team and provide the technical guidance and mentoring for development engineers.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor AWS cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.

*Part-Time or Full-Time Opportunity

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

Be part of a team responsible for designing the next generation of mobile devices. The position includes responsibility for system analysis and HW architecture design for high-speed and low-power interfaces, networking protocols, storage processing, including acceleration of protocols reducing overall power consumption. The job requires collaboration with multiple engineering functions and teams in various geographical locations. It includes identifying system use, requirements definitions, understanding of industry specification for interfaces, operating in industry Standards committees, SW and HW interaction, performance analysis, and more.

Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.

Required Machine Learning Hardware Architect, Hardware, Software Co-Design, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Machine Learning Hardware Architect within the Co-design team, you will serve as a technical lead bridging model architecture innovation and next-generation hardware design. Operating at the highest levels of AI research and engineering, you will define the goal and architectural roadmap for our future machine learning serving and training capabilities. You will guide the integration of ML research such as massive-scale foundation models with advanced silicon architectures to create industry-leading, high-performance, and power-efficient accelerators.
Responsibilities
Define and drive the technical roadmap and architecture for the hardware/software stack to ensure exceptional performance for ML models. Act as the technical liaison across research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
Architect next-generation configurable simulation frameworks and performance models, setting the organizational standard for evaluating complex microarchitectural decisions. Drive high-stakes choices regarding Power, Performance, Area (PPA) and buildability for future chip and system architectures, expertly balancing long-term technological trends with strict product delivery timelines.
Guide system-level performance analysis across highly distributed ML systems, innovating new methodologies to optimize and balance compute, memory bandwidth, and inter-chip network requirements. Their leadership will directly shape the future of high-performance AI infrastructure and hardware-software co-design.
Manage cross-functional partnerships across hardware, compiler development and ML teams.