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We are seeking a highly motivated and experienced System Engineer to join our team and lead the development of sophisticated solutions that push the boundaries of flight

responsibilities:

Lead the development of innovative and complex airborne systems
Develop system requirements that meet customer requirements and product definitions provided by other departments
Facilitate PMO on developing integration plans identifying timelines, resources and equipment requirements to integrate engineering designs into higher level products
Define and lead system level test plans to validate that the engineering designs meet requirements
Collaborate with the R&D and Line of Business managers to ensure timely project delivery
Work as an integral part of the Engineering team in the development of new products and supporting existing products
Define and lead experiments, tests and studies, and/or analytical investigations and provide clear and meaningful results and analysis
Compile and assist in the presentation of test data collected during design validations to a peer group of engineers
Work in collaboration with a multi-disciplined engineering team to develop engineering designs/solutions from initial POC to onsite customer implementations
Contribute to documentation for use in the manufacture, installation, technical support and training related to the final design
Support engineering products through entire life cycle including; assist in installation at customer site, assist in product upgrades and improvements, support of service escalations and product EOL
Oversee technical management of sub-contractors

We are seeking a highly driven, hands-on Operations Production Engineer to join our Operations & Manufacturing team. In this role, you will serve as the primary operational link to our Contract Manufacturers (CMs), drive the end-to-end NPI handoff process into steady-state production, manage legacy product lines, and streamline the production-side RMA pipeline.
If you thrive in a high-growth, fast-paced hardware environment, love diagnosing complex manufacturing challenges, and are passionate about continuous improvement, this is the role for you.
Key Responsibilities:
Contract Manufacturer (CM) Management & Line Ownership:
CM Operations & Execution: Drive day-to-day operational and technical alignment with external CMs to ensure high build execution, product yield, and strict adherence to quality and schedule targets.
Manufacturing Bottlenecks: Identify and resolve yield drops, component shortages/substitutions, or assembly issues directly with vendor engineering teams.
ECO/ECN Release: Oversee engineering change implementation across active production runs at the CM, maintaining clear configuration control.
NPI Composition Handoff & Legacy Product Support:
NPI to Production Handoff: Lead the operational composition and transfer of new product introductions (NPI) from R&D into scalable volume manufacturing at the CM level.
Legacy Product Management: Maintain operational health, sustaining engineering, and end-of-life (EOL) management for legacy product lines to ensure ongoing delivery stability.
Process Documentation: Define standard operating procedures (SOPs), assembly routing, build packages, and work instructions for incoming product variants.
Production RMA Process:
RMA Pipeline Management: Take ownership of the production side of the Return Merchandise Authorization (RMA) process, ensuring rapid triage, dispositioning, and turnaround times.
Feedback Loop: Feed critical quality, design, and manufacturing insights back to R&D and Quality teams to drive design-for-manufacturability (DFM) improvements.
Continuous Improvement:
Yield & Efficiency Optimization: Track key operational metrics (First Pass Yield, Scrap, Cycle Time) and implement engineering fixes to minimize waste and reduce lead times.
Tooling & Fixturing: Coordinate with suppliers to design, validate, or upgrade assembly fixtures, jigs, and test setups.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.
As an Technical Program Manager, you will be the key architect of our silicons operational reality. You wont just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon.
Key Responsibilities
Drive and manage ASIC development and subsystems from concept through to production in collaboration with internal teams and external vendors.
Provide hands-on program management throughout the full development cycle of silicon and firmware, including concept, design, development, fabrication, validation, and production release.
Work closely with the software, hardware, and architecture teams to align with product requirements and ensure all constraints are met.
Lead process improvements across multiple teams and functions to drive better collaboration and efficiency.
Independently manage complex projects with minimal supervision, ensuring timelines and milestones are met.
Deliver high-quality ASIC solutions products while collaborating with product management and architecture teams.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.
As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Physical Implementation & Execution
Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity
Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration
Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust.

Our Network Architecture, Modeling and Performance Insights group is seeking a skilled and driven hands-on Network Modeling Architect to conduct advanced network research and optimization while utilizing and enhancing our advanced simulation tools.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end-to-end performance. You will develop expertise in our simulation tools and write code daily to contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance. If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

 

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generation of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Write production-quality C++ and Python code daily. Hands-on modeling of advanced network topologies, configurations and traffic patterns representing real life AI workloads, and analyze their effect on the system's performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

Required Chip Test Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end to end performance. You will develop expertise in our simulation tools and contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance.

If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generations of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Implement modeling of advanced network topologies, configurations and traffic patterns which represent real life AI workloads, and analyze their effect on the systems performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.