דרושים » חשמל ואלקטרוניקה » Senior CPO System Hardware Engineer

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are looking for a motivated Hardware Engineer to join our Hardware team in Raanana.

You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.

If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.

Principle duties and responsibilities:

Design hardware modules, subsystems and systems for synchronization products.

Develop schematics and guide PCB layout (high-speed, mixed-signal, power).

Select and evaluate components (ICs, power devices, oscillators, interfaces).

Design high-speed interfaces (e.g., 10G/25G Ethernet) with signal integrity considerations.

Contribute to hardware design specifications (HDS) and documentation.

Support system-level integration (HW, FPGA, SW).

Define and execute validation and integration test plans.

Debug complex board and system-level issues (mixed-signal, high-speed).

Perform lab bring-up, measurements, and performance characterization.

Support product transfer to manufacturing (NPI).

Collaborate with manufacturing and test teams for production readiness.

Investigate and resolve issues during production and field operation.

Ensure product reliability, quality, and compliance with applicable standards.

Functional Collaboration.

Work closely with FPGA, software, system, SIT/SVT and mechanical teams.

Participate in design reviews and technical discussions.

Interface with suppliers and external partners as required.

Evaluate and introduce new technologies and components.

Drive improvements in performance, power efficiency, and cost.

Contribute to system architecture discussions and design trade-offs.

We are seeking a talented, high-speed board design expert to own the detailed implementation and industrialization of our next-generation Counter-UAS (C-UAS) processing units.
As we scale to a complex, multi-product ecosystem featuring deep multi-sensor fusion, you will actively participate in shaping digital hardware architectures while leading the hands-on engineering from schematic design to mass production.
This position demands deep expertise in complex, multi-layer carrier board design specifically utilizing Intel processors and COM Express (COMe) architectures, as well as robust simulation and production methodologies.
Key Responsibilities:
Hardware Design Execution: Own the full lifecycle of complex digital hardware boards from schematic capture, component selection, and power distribution network (PDN) design through to high-yield mass production.
Architecture Collaboration: Actively participate in defining the digital hardware architecture, collaborating closely on modular computing strategies, baseboard optimizations, and multi-sensor integration.
Intel & COM Express Integration: Lead the detailed layout and integration of high-performance Intel processors and COM Express (COMe) form factors, managing complex, dense high-speed buses (PCIe Gen 4/5, DDR4/DDR5, 10GbE, USB4).
Simulation & Signal Integrity: Execute rigorous pre- and post-layout Signal Integrity and Power Integrity (SI/PI) simulations to guarantee precise timing margins, stable power delivery, and low-noise performance on dense, fine-pitch BGA footprints.
Production Scale-Up & DFx: Champion Design for Excellence (DFM, DFA, DFT) methodologies, boundary-scan testability, and detailed verification hardware documentation to ensure flawless transfer to manufacturing lines and eliminate field escalations.
Cross-Discipline Collaboration: Work closely with subcontractors (layout) and other R&D disciplines-including FPGA, Embedded SW, Cyber, and Mechanical engineering-to resolve interdisciplinary space, thermal, and noise constraints.

Required RF/HW & System Validation Engineer
Scope:
As an RF/HW Validation Engineer, you will bridge the gap between HW/RF validation and complex system-level testing. You will design, develop, and execute automated and manual test plans to verify the performance, reliability, and compliance of our SDR (Software Defined Radio) architectures and multi-layered tactical systems (including integration with other systems).
Key Responsibilities:
System-Level Testing: Execute end-to-end system testing of counter-drone platforms, verifying the integration of RF hardware, firmware, and complex software-defined radio algorithms under real-world scenarios.
Hardware Product Testing: Test and validate various HW products, including antennas, radar systems, jammers, and related peripherals.
Failure Analysis & Troubleshooting: Debug complex RF anomalies, signal integrity issues, and system bugs down to the component/board level, working closely with RF Design, Board Design, and SW teams.
Documentation: Create comprehensive test plans (ATP/DTP), write test reports, and present data-driven analysis to cross-functional R&D teams to impact the next generation of hardware.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are seeking a high-caliber, multidisciplinary Hardware Systems Architect & Tech Lead to serve as the technical cornerstone of our hardware development and system integration.
In this role, you will bridge high-level system requirements with physical deployment reality, acting as the designated "Tech Lead" driving day-to-day engineering execution.
This role demands a "System of Systems" mindset. Beyond engineering our core SDR and RF hardware architectures, you will orchestrate the physical, logical, and electrical integration of complex tactical sensor suites - incorporating software-defined radios, active/passive radar arrays, electro-optical (EO/IR) cameras, and jamming payloads.
You will steer the hardware through its entire lifecycle (PLCM) while implementing flawless Design for Excellence (DFx) frameworks.
KEY RESPONSIBILITIES:
System of Systems Integration: Architect, model, and define hardware-level interfaces and high-speed data flow paths for multi-sensor integration (SDR, Active/Passive Radar, EO/IR Cameras, and RF Jamming payloads).
Requirements Definition: Translate high-level operational and product demands into detailed, actionable hardware and system-level requirements, Interface Control Documents (ICDs), and structural specifications.
System Modeling: Establish and manage rigorous physical power, thermal, high-speed data bandwidth, and RF link budgets for deeply integrated tactical configurations.
Technical Ownership: Direct day-to-day engineering activities, lead comprehensive design reviews, and serve as the final authority on architectural and hardware design trade-offs.
Product Lifecycle Management (PLCM): Guide hardware products smoothly through the entire lifecycle-from early concept and prototyping to mass production, validation, field deployment, and subsequent obsolescence management.
Cross-Functional Orchestration: Align and coordinate specialized teams across RF/Analog, high-speed digital, FPGA, embedded software, and mechanical engineering to achieve seamless hardware/software synergy.
Test Strategy Definition: Architect and define the end-to-end testing, verification, and validation (V&V) strategy for complex hardware-software systems.
Progressive Integration: Design and oversee methodical integration plans, successfully migrating subsystems from standalone bench testing to full "System of Systems" integration.
System Verification: Oversee high-reliability Hardware-in-the-Loop (HIL) testing, RF performance verification, and automated test regression setups.
Operational Validation: Partner with field testing and QA teams to design real-world tactical validation scenarios (including drone flight trials and complex RF interference environments) to ensure top performance in the field.
DFx Implementation: Drive critical design decisions optimizing for manufacturability (DFM), automated testing (DFT), reliability (DFR), and target cost (DFC) without sacrificing tactical performance.

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

We are looking for a Distinguished Engineer to help shape the future of AI infrastructure. As part of our advanced development and research efforts, you will drive technical vision and innovation across the AI software stack, spanning GPU computing, RDMA, NVLink, storage, and large-scale distributed systems. You will research next-generation system designs, influence product and platform direction, and help define how massive-scale AI environments are built, optimized, and operated through hardware-software co-design.

What youll be doing:

Research, define, and drive co-design solutions across AI software stacks involving GPU computing, RDMA networking, NVLink interconnects, storage, and large-scale distributed infrastructure.

Lead deep technical investigations and proof-of-concept development in areas related to distributed AI, deep learning systems, high-performance computing, virtualization, memory management, and large-scale systems design.

Work closely with multiple teams across us to advance next-generation AI infrastructure technologies and influence cross-stack co-design decisions.

Analyze end-to-end system bottlenecks and opportunities across compute, networking, memory, and storage layers to improve performance, scalability, and efficiency.

Guide the design of environments that support massive-scale AI training and inference workloads in production.

We are seeking a Senior RF Systems & Design Engineer to join our RF team and help architect and industrialize our next-generation Counter-UAS (C-UAS) multi-product hardware ecosystem. In this role, you will bridge the gap between high-level Software-Defined Radio (SDR) concepts and high-yield mass production. You will guide modular architectural layouts, define core interfaces for internal and external sensors, implement critical DFx methodologies, and mentor junior talent within an evolving, fast-paced technical landscape
Key Responsibilities
1. Architecture & System-Level Design
Architect modular, RF transceiver systems and define cascading link budgets (NF, Gain, IP3, P1dB) from antenna to converter.
Design advanced wideband SDR front-ends and direct RF sampling topologies tailored to defeat dynamic threats.
Establish Interface Control Documents (ICDs) and hardware abstraction standards to seamlessly integrate 3rd-party subsystems (Radar, EO/RF).
2. Detailed HW Design, Simulation & Validation
Lead schematic capture, high-frequency/high-density PCB layout supervision, and component choices (PAs, LNAs, synthesis filters).
Perform electromagnetic and circuit-level modeling (ADS, HFSS, or equivalent) to resolve structural EMI/EMC and co-site isolation issues.
Formulate strict engineering Verification & Validation (V&V) plans, overseeing environmental and compliance certifications.
3. DFx & Production Scale-Up
Champion Design for Manufacturing/Assembly/Test (DFM/DFA/DFT) workflows to ensure stable, repeatable high-yield production loops.
Define line-calibration algorithms, built-in self-tests (BIST), and leverage Statistical Process Control (SPC) data to reduce production and field escalations.
4. Leadership & Mentorship
Collaborate across disciplines (Mechanical, Digital, Cyber-Software) to systematically resolve thermal, power, and high-speed noise friction points.
Act as a primary technical mentor for junior engineers, implementing standard product lifecycle (PLC) gating and best practices.